Fujitsu Corporation

Hideki Ishida

Kazuaki Oishi

Kohtaroh Gotoh

Hirohito Higashi

Megumi Oono

Hirotaka Tamura

Hisakatsu Yamaguchi

Hideki Takauchi

Takaya Chiba

Shunichiro Masaki

Yoshie Kanamori

Masaaki Kaneko

Takuya Saze

An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is &#xbd; unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.

Adaptive equalizer circuit

A semiconductor integrated circuit device has a first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, a resistor connected in series between a first power-source line and a second power-source line, and a third MIS transistor of the first conductivity type. The third MIS transistor has a gate connected to a node where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node where the second MIS transistor and the resistor are connected together.

Semiconductor integrated circuit device enabling to produce a stable constant current even on a low power-source voltage

An oscillator for ensuring the phase relationship between two resonant circuits coupled by a coupling circuit. A first resonant circuit outputs two signals having different phases, and a second resonant circuit outputs two signals having different phases. The coupling circuit includes a plurality of inverters connected in a ring manner, and couples the first resonant circuit and the second resonant circuit such that the two signals output from the first resonant circuit and the two signals output from the second resonant circuit have different phases. A filter is connected to the input side of each of the plurality of inverters. With this structure, a signal output from each of the plurality of inverters has either a phase lead or a phase lag according to the phase characteristics of the corresponding filter, and thus the phase relationship between the first resonant circuit and the second resonant circuit is ensured.

Oscillator and semiconductor device

A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in amplitude.

Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude

A clock recovery circuit has a phase comparator circuit, a phase adjusting circuit, and a duty cycle correction circuit. The phase comparator circuit carries out phase comparison between an input signal and an output signal, and outputs a phase control signal proportional to a phase difference between the input signal and the output signal. The phase adjusting circuit receives the phase control signal from the phase comparator circuit, adjusts the phase of the input signal, and produces the output signal, and the duty cycle correction circuit receives the output signal from the phase adjusting circuit, and corrects the duty cycle of the output signal.

Clock recovery circuit for high-speed data signal transmission

A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.

Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction

A frequency measurement circuit measures a frequency of an input signal. The frequency measurement circuit includes a frequency measurement unit for counting a reference clock during a counting period having a predetermined number of waves of the input signal. The frequency measurement unit counts the reference clock by using a lighter amount of weighting to each count at a starting time and an ending time of the counting period than the amount of weighting at the other times of the counting period.

Frequency measurement circuit

A frequency measurement circuit comprises a plurality of frequency measurement units , K each of which counts a reference clock Cb during a counting period having a predetermined number of waves of an input signal Cin, each of the frequency measurement units counts the reference clock, with shifted counting periods, respectively. Moreover, an adder is provided to add the counted numbers of the plurality of the frequency measurement units. By shift the counting periods, even if the phase of the input signal agrees with the phase of the reference clock at the time counting starts and at the time counting ends on a certain frequency measurement unit, there is scarcely any possibility of agreement of the phases on other frequency measurement units. Therefore, by utilization of the added number of counts, frequency can be measured with high accuracy. In addition, by making the counting periods being shifted with overlaping each other, extension of the measurement time is not required any longer.

A bias current IB additionally provided to a current-controlled circuit in a PLL circuit is the sum of bias currents IB and IB which are generated by a bias adjustment circuit ( and ) and a bias current generating circuit ( and ), respectively. The bias adjustment circuit adjusts the bias current IB in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit generating a bias voltage VT and a circuit converting the VT into a current IB wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.

Automatic bias adjustment circuit for use in PLL circuit

A current source switch circuit has at least one transistor forming part of a current source, and one switch for controlling the supply of an electric current from the transistor to a load. A voltage application unit applies a voltage having a value in an operation state as a current source to a transistor forming part of the current source while no electric current is provided from the switch to the load.

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Kawasaki, Japan

Hideki Ishida