Kabushiki Kaisha Toshiba

Hideki Ishibashi

Hiroyuki Ibe

Osamu Kinoshita

Takehiko Atsumi

Kazuyoshi Matsuno

Takako Mori

In addition to a main monitor/control module, sub-monitor/control modules are provided, which monitor the operating conditions of transmission sections in real time through a CPU bus. The main monitor/control module collects monitor data from each sub-monitor/control module at a given timing through a LAN and processes the monitor data collected.

Digital signal transmission apparatus

In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors of a first synchronization detecting circuit detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit holds outputs of the pattern detectors, and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit is delayed by a time required for the above-mentioned processing, and supplied to a selector, which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal.

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Fuchu, Japan

Hideki Ishibashi