Kabushiki Kaisha Toshiba

Hideki Inokuma

Nobuo Nakamura

Hirofumi Yamashita

Ikuko Inoue

Tetsuya Yamaguchi

Hisanori Ihara

Hidetoshi Nozaki

Hiroshi Naruse

Hidenori Shibata

Akiko Nomachi

Yoshiyuki Shioyama

Masako Hori

Akira Makabe

Seigo Abe

Hideaki Aochi

Masaru Kito

Ryota Katsumata

Takayuki Ishikawa

Kazuhiko Yamamoto

Shosuke Fujii

Akira Takashima

Daisuke Matsushita

Yoshifumi Nishi

Yusuke Arayashiki

Hidenori Miyagawa

Toshiharu Tanaka

Yoichi Takegawa

Takashi Haimoto

Masaru Kido

A semiconductor device includes a substrate, a plurality of element regions that are partitioned in a line-and-space shape and extend in a first direction in the substrate, a plurality of selection gates that are formed on the substrate to extend in a second direction intersecting the first direction. In addition, the semiconductor device includes a contact region that includes a plurality of contact plugs which are provided between two selection gates adjacent to each other and are connected to the respective element regions in the substrate. Further, the contact plug includes an upper portion and a lower portion. The upper portion has a first width and is formed of a first conductive film and a second conductive film. The lower portion has a second width smaller than the first width and is formed of the first conductive film.

Semiconductor device

A manufacturing method includes forming a laminated body on a substrate. A mask layer is formed on the laminated body, and then a portion of the mask layer is removed to form an opening. Then, using the mask layer as a template, a first portion of the laminated body is removed to expose a portion of the substrate beneath the laminated body. The substrate is processed to alter the ratio between the size of mask opening and the removed first portion. A variable resistance layer is then deposited on exposed portions of the mask layer, the laminated body, and the substrate. Then the variable resistance layer is processed to remove at least a portion covering the substrate to permit contact with the underlying substrate. A second electrode layer is deposited to fill the removed portions of the laminated body.

Manufacturing method of non-volatile storage device, and non-volatile storage device

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

Nonvolatile memory device and method for manufacturing same

According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.

Memory device

In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconductor substrate adjacent to both sides of the gate electrode is removed beyond the lower part of the sidewall insulating film and to the underside of the gate electrode. Then, the gate insulating film exposed in the remove part is removed. An impurity-doped semiconductor layer is formed in the part where the semiconductor substrate and the gate insulating film have been removed.

Semiconductor device and a method of manufacturing the same

According to an aspect of the invention, there is provided a semiconductor device including a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers, a first insulating film and a second insulating film formed on source/drain regions and gate electrodes of the first element and the second element, the first insulating film having tensile stress with respect to the first element, and the second insulating film having compression stress with respect to the second element, and sidewall spacers of the gate electrodes of the first element and the second element, at least portions of the sidewall spacers being removed, wherein at least one of the first insulating film and the second insulating film does not close a spacing between the gate electrodes of the first element and the second element.

Method of fabricating semiconductor device having semiconductor elements

A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.

Semiconductor device having trench capacitor and fabrication method for the same

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a pdiffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the pdiffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the pdiffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the pdiffusion layer to a position below the gate electrode.

Solid-state image pickup apparatus

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p diffusion layer to a position below the gate electrode.

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Yokohama, Japan

Hideki Inokuma