Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electronic Corporation

Hideki Haruguchi

Tetsujiro Tsunoda

Yoshifumi Tomomatsu

Takuya Hamaguchi

Tomohito Kudo

Katsumi Satoh

Yasuo Ata

Youichi Ishimura

Toshiki Fukasawa

Yoshihumi Tomomatsu

A silicon substrate has first to fourth semiconductor regions. The third semiconductor region is separated from the first semiconductor region of a first conductivity type by the second semiconductor region of a second conductivity type. The fourth semiconductor region of the second conductivity type is separated from the second semiconductor region by the third semiconductor region. A first electrode is provided on a first surface. A barrier metal layer is provided on a first portion of a second surface. A second electrode is provided on the second surface, and is separated from the first portion of the second surface by the barrier metal layer. The second electrode includes an aluminum-silicon (Al—Si) layer in contact with a second portion of the second surface, and an Al layer separated from the second portion of the second surface by the Al—Si layer.

Power semiconductor device including a substrate and an electrode having multiple layers with one of the upper layers being in direct contact with a portion of the surface of the substrate

A third dummy trench () is orthogonal to the first and second dummy trenches () in the dummy cell region of a substrate end portion. An interlayer insulating film () insulates the p-type diffusion layer () in the dummy cell region of a substrate center portion situated between the first and second dummy trenches () from the emitter electrode (). The third dummy trench () separates the p-type diffusion layer () in the dummy cell region of the substrate center portion from the p-type diffusion layer () in the dummy cell region of the substrate end portion connected to the emitter electrode (). A p-type well layer () is provided deeper than the third dummy trench () in the substrate end portion. The third dummy trench () is provided closer to a center of the n-type substrate than the p-type well layer ().

Semiconductor device including active and dummy cell regions

An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.

Semiconductor device

An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

Insulated gate bipolar transistor having contact region with variable width

A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.

Semiconductor device with enhanced switching speed and method for manufacturing the same

An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor ( ) is connected in parallel to a diode ( ) made of silicon carbide. Although a resistive component of the diode ( ) varies widely with turn-on and turn-off of the diode ( ), connecting the resistor ( ) in parallel to the diode ( ) allows suppression of variations in a resistive component of an LCR circuit formed by the diode ( ) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Silicon carbide semiconductor switching device

A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.

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Tokyo, Japan

Hideki Haruguchi