Nec Corporation

Sony Corporation

Mitsubishi Electric Corporation

Renesas Electronics Corporation

Sony Interactive Entertainment Inc.

Nec Electronics Corporation

Sony Computer Entertainment Inc.

Hideki Hara

Kazumi Sato

Takashi Akai

Toshiyuki Nishihara

Hitoshi Ebihara

Katsuya Nakashima

Kazuhiko Sanada

Yukihisa Tsuneda

Hideki Sugiyama

Toshifumi Nomura

Takahisa Kojima

Masakazu Mokuno

Masashi Endo

An input control device includes a touch information acquiring unit for acquiring touch information from a touch panel, a touch angle calculating unit for calculating an angle of a touched area on the basis of the touch information acquired by the touch information acquiring unit, an operating direction estimating unit for estimating the direction of an operator who has touched the touch panel, on the basis of both the angle of the touched area, the angle being calculated by the touch angle calculating unit, and an angle threshold, a detection information acquiring unit for acquiring detection information from a sensor for detecting a part of the operator's body, a relative position estimating unit for estimating a relative position of the part of the operator's body with respect to the touch panel on the basis of the detection information acquired by the detection information acquiring unit, and a threshold correcting unit for correcting the angle threshold on the basis of the relative position of the part of the operator's body with respect to the touch panel, the relative position being estimated by the relative position estimating unit.

Input control device, input control method and display device that estimate operator position relative to a touch panel

A programmable device is disclosed which includes: a circuit data setting section configured to set a logical configuration in a processing circuit using first setting information retrieved from a memory; and a communication status monitoring section configured to determine whether communication is established between the processing circuit and a host computer using the setting made by the circuit data setting section. If it is determined that the communication is not established, the circuit data setting section retrieves from the memory second setting information different from the first setting information to again set a logical configuration in the processing circuit on the basis of the second setting information.

Programmable device, information processing device, and control method for processing circuit of programmable device

A nonvolatile semiconductor memory comprises a first memory cell transistor, a second memory cell transistor, a connection layer, protrusion portions and a contact portion. The first memory cell transistor comprises a first gate electrode formed above a first channel region, and a second gate electrode formed on a side of the first gate electrode through an insulating film. The second memory cell transistor comprises a third gate electrode formed above a second channel region, and a fourth gate electrode formed on a side of the third gate electrode through an insulating film and facing the second gate electrode. The connection layer connects the second gate electrode and the fourth gate electrode. The protrusion portions are formed of a material different than that of the second and fourth gate electrodes, and are formed on both ends of the connection layer. The contact portion is formed on the connection layer.

Method of manufacturing nonvolatile semiconductor memory with backing wirings

A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

File storage apparatus for storing file data and management information

An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon.

Image processing apparatus and method

A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Structure of a capacitive element of a booster circuit included in a semiconductor device and method of manufacturing such a structure

The present invention provides a method of forming a diffusion layer which extends on bottoms and side walls of trench grooves as well as on top portions of ridged portions separating the trench grooves, and the trench grooves being separated by ridged portions of the substrate so that the trench grooves and the ridged portions are aligned between adjacent two of gate electrode structures, the method comprising the steps of: carrying out a first ion-implantation in a vertical direction to introduce an impurity into the bottoms of the trench grooves and into top portions of the ridged portions by use of gate electrode structures; forming side wall insulation films on side wails of the gate electrode structures; and carrying out a second ion-implantation in an oblique direction with a rotation of the substrate by use of the gate electrode structures and the side walls.

Method of forming a semiconductor memory device having source/drain diffusion layers with a reduced resistance

There is provided a storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the area via a gate insulating film, and a control gate formed on the floating gate via an interlayer insulating film, the method comprising steps of: applying a predetermined positive voltage to a bit line connected to the drain area and a word line connected to the control gate, injecting an electron to the floating gate, and writing data to a selected memory cell; applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to the semiconductor substrate or the source area, discharging the electron accumulated in the floating gate of the selected memory cell, and performing data erasing; and after the data erasing, applying the predetermined positive voltage necessary for injecting the electron to the floating gate from a channel area in the vicinity of the source area to the common source line, and performing write-back of the memory cell erased excessively.

Storage method of semiconductor storage apparatus

The present invention provides a network apparatus for a network of ring topology configuration in which an insertion of an I/O card automatically ring-connects the I/O card and a removal of the I/O card automatically leaves the empty position ring-connected. A connector,which is ring-connected to a network includes connection means to be inserted to intervene a signal line. The connection means has a first terminal member and a second connection member. In a first state of the connection means, the first terminal member is in contact with the second terminal member so as to establish an electrical connection between the first terminal member and the second terminal member. In a second state of the connection means, the first terminal member is mechanically disconnected from the second terminal member, which is associated with that the first terminal member is brought into contact with a first connection member of a node so as to establish an electrical connection between the first terminal member and the first connection member, and the second terminal member is brought into contact wint a second connection member of the node so as to establish an electrical connection between the second terminal member and the second connection member.

Connector, data processing apparatus, and network apparatus

A semiconductor device includes a field oxide film, a plurality of word lines, an insulating interlayer film, a plurality of contact holes, a plurality of protective diffusion layers, a plurality of common contact holes, and a plurality of metal plugs. The field oxide film is formed on a silicon substrate having one conductivity type. The word lines are formed by patterning on the field oxide film. The insulating interlayer film is formed on the field oxide film to cover the word lines. The contact holes are formed in the field oxide film to be self-aligned with the word lines. The protective diffusion layers have an opposite conductivity type and are formed on a surface of the semiconductor substrate to correspond to the contact holes. The common contact holes are formed in the insulating interlayer film to extend across the word lines and the protective diffusion layers. The common contact holes are formed at a depth to reach the protective diffusion layers while partly exposing the word lines. The metal plugs fill the common contact holes to electrically connect the protective diffusion layers and the word lines with each other. A method of manufacturing a semiconductor device is also disclosed.

Method of manufacturing floating gate type transistor

In a data erase operation of the present invention, a drain terminal is opened. A negative voltage of about -10 V and a voltage of about 5 V are applied to a cell gate and a source terminal, respectively. The voltage of about 1-2 V is applied to a P well terminal and an N well terminal. A ground potential is provided to a substrate. A voltage which is lower than the voltage of the source terminal and higher than the substrate voltage (ground voltage) is applied to a P well and an N well between a source diffusion layer and the substrate. Thus, an electric field generated between a source and a floating gate realizes the erase by means of F-N tunneling.

Method of erasing data in nonvolatile semiconductor memory devices

Semiconductor device and method of manufacturing the same

The semiconductor memory device includes a first conductivity type semiconductor substrate, a tunnel gate oxide film formed on the semiconductor substrate, a floating gate formed on the tunnel gate oxide film, and a control gate formed on the floating gate. The semiconductor substrate includes second conductivity type source and drain regions, a second conductivity type lightly doped region formed so that it covers the source region, and a first conductivity type heavily doped region formed so that it covers at least the drain region and overlaps at least partially with the lightly doped region beneath the floating ate. The semiconductor memory device prevents excessive data erasure regardless of the dispersion in thickness of the tunnel gate oxide film, thereby preventing misreading and enhancing reliability of operation.

Semiconductor memory device that converges a floating gate threshold

A floating gate type field effect transistor increases the threshold during an application of a write-in pulse to the control gate electrode thereof so as to inject hot electrons into the floating gate electrode, and the write-in pulse is decayed along a waveform having a gradient smaller than a gradient of a pulse signal assumed to take place in a source/drain region of a non-selected floating gate type field effect transistor sharing the selected word line with the selected floating gate type field effect transistor, thereby preventing the non-selected floating gate type field effect transistor from the gate disturb phenomenon.

Method of writing data into electrically erasable and programmable read

Gate insulating film of a memory cell in a nonvolatile semiconductor memory devices is protected from a plasma damage by a residual side wall insulating film. After forming field oxide films and first gate insulating films, gate structures each including a control gate, a second insulating film and a floating gate is formed. A fourth insulating films are deposited on the entire surface and ion-etched to leave residual side wall insulating films at the side walls of each of the gate structures. The residual side wall films protect the first gate insulating films and silicon substrate from a plasma damage. At least one of the source and drain is formed in a LDD structure due to the ion-implantation through the residual side wall insulating films. Resistance characteristics to breakdown due to a high voltage can be improved by reducing deterioration of the first gate insulating films. Other electric characteristics can be improved by the LDD structure.

Growing community of inventors

Tokyo, Japan

Hideki Hara