Fujitsu Corporation

Sony Corporation

Spansion Llc.

Powerchip Technology Corporation

Powerchip Semiconductor Corporation

Powerchip Corporation

Cypress Semiconductor Corporation

Hideki Arakawa

Masaru Yano

Hiromi Kawashima

Riichiro Shirota

Hidehiko Shiraiwa

Mototada Sakashita

Te-Chang Tseng

Chun-Yi Tu

Jaeyong Park

Satoshi Torii

Tomofumi Kitani

Takashi Miida

Tzung Ling Lin

Takeshi Nakayama

Ching Sung Yang

Akira Tanaka

Akira Ogawa

Takashi Ito

Satoru Kawamoto

Makoto Senoo

Mitsuo Higuchi

Kenshiro Arase

Hiroaki Watanabe

Yoshiki Okumura

Takao Nozaki

Nobuhiko Ito

Yutaka Sekino

Masaichi Shinoda

Hajime Ishikawa

Yoshinobu Higuchi

Takashi Narikiyo

Hajime Aoki

Akitomo Nakayama

Masaru Miyashita

Yamasaki Kyoji

Teruaki Maeda

Takuo Ito

Keisuke Kanazawa

Kazuhisa Nakamura

Yoshiaki Shinmura

A high voltage generating circuit includes a charge pump circuit and an output voltage control circuit. The charge pump circuit raises a voltage to a high voltage higher than a power supply voltage. The output voltage control circuit controls the voltage to make the raised high voltage to be a predetermined target voltage. The output voltage control circuit includes at least two offset free comparator circuits, or at least one offset free comparator circuit and at least one differential amplifier. The offset free comparator circuit includes a coupling capacitor, a differential amplifier and a plural switch. The coupling capacitor inputs a voltage corresponding to the high voltage. The differential amplifier compares a voltage from the coupling capacitor with a predetermined reference voltage and outputs a comparison result voltage to the charge pump circuit. The switches are connected to the differential amplifier to cancel an offset of the differential amplifier.

Voltage generating circuit and regulator circuit for precisely control predetermined high voltage

A negative reference voltage generating circuit includes a switched capacitor circuit having a capacitor connected to a first and a second nodes, a first and a second switches connected to the first node, a third and a fourth switches connected to the second node; and a control circuit, generating a first to a fourth control signals to control the first to the fourth switches respectively. The control circuit applies a preset positive reference voltage to the first node to charge the capacitor during a first period, and outputs a negative voltage from the second node based on the voltage charged to the capacitor during a second period different from the first period. By repeating the first and the second periods, an inverting negative voltage of the positive reference voltage that is outputted from the second node is used as a negative reference voltage.

Negative reference voltage generating circuit

A negative reference voltage generating circuit generating a negative reference voltage is provided, including a differential amplifier, a first diode, second diodes, and a third resistor. The differential amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal, and is driven by a positive and a negative power voltages. The output terminal is connected with the non-inverting input terminal via a first resistor and connected with the inverting input terminal via a second resistor. The first diode includes a cathode connected with the non-inverting input terminal of the differential amplifier and an anode connected with a ground. The second diodes respectively include a cathode connected with a predetermined connection point and an anode connected with the ground, and are connected in parallel. The third resistor is connected between the connection point and the inverting input terminal of the differential amplifier.

Negative reference voltage generating circuit and system thereof

There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask pattern by etchback of a deposited second film, removing the first mask pattern, and forming a second mask pattern composed of the first sidewall films and second sidewall films defined by etchback of a deposited third film. It is possible to form a stripe pattern with the line width and the line space thereof having the same sizes and at a pitch the same as the minimum process size determined by the photolithographic performance, thereby enabling fabrication of a semiconductor device with a high degree of integration.

Transistor formation method using sidewall masks

In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

Programming method for NAND flash memory device to reduce electrons in channels

A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line.

Nonvolatile semiconductor storage device and control method thereof

A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array. In the stage before an erasing pulse adding in an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

Nonvolatile semiconductor memory device and write-in method thereof

A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.

Memory device and data reading method

An integrated circuit is provided. The integrated circuit includes a memory device and a discharge circuit. The discharge circuit discharges the well voltage line and the first voltage line of the memory device after the end of the erasing period and includes a first and second switch circuit and a first and second control voltage supplier. The first switch circuit is coupled between the well voltage line, the first voltage line and a second supplier. The second switch circuit is coupled between the first switch circuit and a reference voltage. The first control voltage supplier is coupled to the first switch circuit and supplies a first control voltage to turn on the first switch circuit during a first discharge period. The second control voltage supplier is coupled to the second switch circuit, and supplies a second control voltage to turn on the second switch circuit during a second discharge period.

Integrated circuits and discharge circuits

A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during which a DC-DC converter section supplies a boosted voltage increased from the external voltage to an internal bias line for supplying a bias voltage to the memory cell array, a non-boosted voltage supply section for supplying a non-boosted voltage equal to or less than the external voltage is in its inactive state. In the period during which the non-boosted voltage supply section supplies a non-boosted voltage to the internal bias line, the DC-DC converter section is in its inactive state. In the period during which a boosted voltage is supplied to the internal bias line, the DC-DC converter section is used for ensuring sufficient power supply ability, and in the period during which the non-boosted voltage is supplied to the internal bias line, the DC-DC converter section can be kept in its inactive state. Thus, the power consumed by the DC-DC converter section can be saved in the period during which the supply of a boosted voltage is unnecessary.

Storage device and control method thereof

A memory programming method is provided. A first programming operation is performed to program a multi level cell from an initial state to a first target state, which corresponds to a storage data and has a first threshold voltage range. A flag bit of the NAND flash is set to a first state to indicate that the first programming operation has been performed. A second programming operation is performed to program the multi level cell from the first target state to a second target state, which corresponds to the storage data and has a second threshold voltage range. The flag bit is set to a second state to indicate that the second programming operation has been performed.

Memory programming method and data access method

A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

SONOS memory with inversion bit-lines

A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S).

Semiconductor device and method of controlling the same

A control method for a nonvolatile storage device having a storage mode in which in a memory cell provided with a trapping dielectric layer 1-bit data is stored depending on the presence or absence of charge in a first trapping region. In a dynamic reference cell initialization operation, a charge accumulation operation is performed, as a preset operation in the initialization operation, on second trapping regions of first and second dynamic reference cells to a charge accumulation operation on a second trapping region of the memory cell. In addition, at the time of data rewrite, preprogram verification and preprogramming are performed on the first trapping regions. This makes it possible to shorten the time taken for initialization and data rewrite.

Controlling a nonvolatile storage device

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Yokohama, Japan

Hideki Arakawa