Panasonic Corporation

Hideki Aoyagi

Michiaki Matsuo

Hitoshi Asano

Suguru Fujita

Kazuya Toki

Takenori Sakamoto

A received pulse signal based on an on-off keying modulation scheme is alternately sampled by AD conversion sections operated by a clock signal whose frequency is one-half of a transmission rate. In the synchronization, amounts of delay in sampling timing adjustment sections are made different from each other, whereby phases of two different points in a symbol pulse are sampled. An amount of delay in a variable delay section is adjusted in accordance with a result of comparison of the sampled values, thereby achieving synchronization. At the time of demodulation, the amount of delay in the variable delay section is held, and the amounts of delay in the sampling timing adjustment sections are switched to the same value, and the symbol pulse is alternately sampled. The sampled values are subjected to threshold value determination, and the determination result is subjected to parallel-to-serial conversion, whereby a demodulation output is acquired.

Pulse-sync demodulator

The present invention has an object to provide a wireless apparatus which is capable of correctly sampling a waveform of a pulse even when a shape of the pulse is varied. A synchronizing apparatus for causing an input signal to be synchronized with a clock signal is equipped with sampling unit, and delay control unit. The sampling unitandsample the input signal at first sampling timing and second sampling timing, which are separated from each other in a predetermined time interval. The delay control unitshifts both the first and second sampling timing during synchronous pull-in operation, and also, narrows the interval between said first and second sampling timing during synchronous follow-up operation. A synchronous status judging unitjudges whether or not the input signal is synchronized with the clock signal based upon a phase error amount outputted from a phase error calculating unit, and outputs the synchronous status to a delay amount control unitThe delay amount control unitcontrols to increase/decrease delay amounts which have been presently set in variable delay devicesandbased upon the phase error amount outputted from the phase error calculating unitand the synchronous status outputted from the synchronous status judging unit

Wireless apparatus

A pulse signal reception device of a comparatively simple configuration detects a signal sampled at an optimal clock timing for a pulse modulation signal having a signal width shorter than a symbol frequency. In this device, a time division unit () samples a data signal at a clock signal rise edge and outputs the sampled data signals to counters (-to-), respectively. The counters (-to-) count the number of High levels when the data signal becomes High level within a predetermined period, and a maximum value detection unit () outputs maximum data string information on a data string counted by a counter in which the maximum number of High levels has been detected among the counters (-to-) to a selection data judgment unit (). The selection data judgment unit () judges which data string sampled at a particular timing is to be selected as a demodulation data string.

Pulse signal reception device, pulsed QPSK signal reception device, and pulse signal reception method

A pulse transmitter having a relatively simple structure and generating a pulse modulating signal even at a high transmission rate. In the pulse transmitter, a symbol pulse generating part () generates a symbol pulse of amplitude level &#x3b2; when data Sis '0,' and that of amplitude level &ggr; when data Sis '1' in the first pulse slot section, the data pulse generating part () generates a data pulse of amplitude levelwhen data Sto Sn is &#x201c;0,&#x201d; and that of amplitude level &#x3b1; when data Sto Sn is &#x201c;1&#x201d; in a later pulse slot section. The relationship of the amplitude levels keep the relation &#x3b1;&#x3c;&#x3b2;&#x3c;&ggr. An adder () adds the symbol pulse and the data pulse and outputs the sum as a pulse modulating signal.

Pulse transmitter, pulse receiver, pulse transmitting method, and pulse demodulating method

It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay blockhaving N (N is a natural number) delay elementsto, and N selectorsto; a variable delay blockhaving N delay elementsto, and N selectorsto; and a selector. After selection signalstoandtoare changed, and after an output timing of a delay amount set by the variable delay blocksis attained, the signal to be output is switched by the selector, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

Growing community of inventors

Miyagi, Japan

Hideki Aoyagi