Mitsubishi Denki Kabushiki Kaisha

Hideki Ando

Chikako Ikenaga

Hirohisa Machida

Takahiro Miki

Takeo Nakabayashi

Masao Nakaya

Harufusa Kondo

Harufusa Kondou

Hiromi Notani

Chikako Nakanishi

Harlifusa Kondoh

The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.

Superscalar processor with direct result bypass between execution units having comparators in execution units for comparing operand and result addresses and activating result bypassing

A processing device executes an instruction speculatively, and execution result of the instruction becomes valid when all the predictions about true/false of branch condition are correct, and the instruction has a commit condition indicating the number of branch conditions. The processing device includes a commit condition decoder for decoding the commit condition; ALU's; a sequential register file for sequentially holding data obtained from ALU; a shadow register file for speculatively holding data obtained from the ALU; true/false register having determination entries, each of which holds undetermined information if true/false of the corresponding branch condition is not yet determined, holds true information if the corresponding branch condition is true, and holds false information if the corresponding branch condition is false; execution control circuit for comparing true/false of an instruction decode entry provided from the commit condition decoder with true/false of the determination entry and controlling the sequential register file to sequentially hold data if they correspond with each other or otherwise controlling the shadow register file to speculatively hold data; and a commit control circuit for comparing true/false of the instruction decode entry with true/false of the determination entry and transferring the data held in the shadow register file to the sequential register file if each true/false of the instruction decode entry coincides with true/false of the corresponding determination entry.

Compiler for converting source program into object program having

A technique for providing information about the relationship between circuits and the amounts of power consumed by the respective circuits to control a heat-sensitive circuit with higher accuracy is disclosed. A decoder (6a) causes an ALU power evaluation counter (7a) to count when a control code applied thereto is not an ALU control code. The ALU power evaluation counter (7a) counts the number of control codes which do not operate an ALU (5a). A multiplier (14) multiplies the output from the ALU power evaluation counter (7a) by a predetermined number to provide the result to an adder (10). The adder (10) adds the results from multipliers (14-16) together to store the result in a total power evaluation register (11). The smaller the value stored in the total power evaluation register (11), the greater the amount of heat generated. A DRAM refresh control circuit (12) shortens a refresh cycle so that a DRAM (13) is frequently refreshed.

System for monitoring power consumption of semiconductor devices

An instruction cache memory provides a low probability of occurrence of cache error. The instruction cache memory includes an advance read function with an instruction cache for providing/receiving instruction formation in block unit to/from a main memory, an instruction analysis section for predicting whether it is necessary to read out a next block from the main memory by analyzing the instructions included in the block read out from the main memory presently being transferred to the instruction cache, and circuits for reading out the next block from the main memory to transfer to the instruction cache when predicted to be necessary by the instruction analysis section. Prediction is done by judging if a branch predict signal produced within the instruction cache memory is present or not, judging the branch destination to be within the block or in the next block when the branch instruction is detected, and judging whether the branch operation is a forward branch or a backward branch.

Instruction cache memory apparatus with advanced read function that

A parallel processing apparatus of a superscalar type includes an instruction decoding stage which decodes four instructions simultaneously fetched from an instruction memory and issues instructions which allows simultaneous execution to related function units. The instruction decoding stage includes an instruction decoder which decodes the instruction and issues the instructions allowing simultaneous execution to the function units, and a queue which queues and stores the instructions fetched from the instruction memory. This instruction decoding stage also includes a scope logic which forms a read queue address for reading the instructions of the queue in accordance with the number of issued instructions in the instruction decoder and whether a branch is generated by a branch instruction, and a queue top logic which forms a write address in the queue in accordance with a storage state of an unissued available instruction in the queue. Instructions are read from four successive addresses starting from the read address. Fetched instructions are stored in four addresses in the queue starting from the write address. Four instructions to be decoded are always supplied to the instruction decoder in accordance with an issue state of the instructions. Four instructions are always fetched from the instruction memory and queued. Therefore, the instructions can be efficiently supplied to the instruction decoder in accordance with the execution state of the instructions.

Pipelining device in a parallel processing apparatus and an instruction

The parallel processing microprocessor includes a register file for storing a plurality of data and a plurality of groups of bit sliced circuits provided corresponding to a plurality of data. Each group of bit sliced circuits consists of a plurality of bit sliced circuits. The plurality of bit sliced circuits are arranged collectively. The plurality of bit sliced circuits are arranged corresponding to a plurality of instructions and processing in parallel a corresponding one of the plurality of data in response to the plurality of instructions.

Microprocessor with reduced area coupling a register file with a

A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in the branch-delay slot are those fetched in a period from fetching of the branch instruction till the execution of the branch instruction. Instructions are prefetched from an instruction memory into a queue memory. The queue memory includes a plurality of blocks of storage units. Instructions in the same block as a branch instruction and subsequent to the branch instruction, and instructions in the block adjacent to the block including the branch instruction provide the branch delay slot for the branch instruction. A parallel processing unit operable in a predicted branch method includes a queue memory including a plurality of entries, each of which includes an instruction and a flag indicating that an associated instruction is executed according to a prediction of a branch. This flag is utilized to control execution and non execution of an associated instruction.

Parallel processing unit which processes branch instructions without

System for speculatively executing instructions using multiple commit

The microprocessor which processes instructions with commit conditions in parallel includes a sequential register file for storing result data of sequential instructions; a shadow register file for storing result data of speculative instructions; a TF register including a plurality of entries each holding information indicating that the commit condition is 'true', 'false' or 'undetermined'; an execution control circuit for comparing the commit condition and a corresponding entry in TF register, storing the result data in sequential register file if the instruction is sequential, and storing the result data in shadow register file if the instruction is the speculative; and a commit control circuit for storing the commit condition and transferring the result data stored in the shadow register file to sequential register file when a coincidence is found between true/false for the commit condition and true/false in TF register 10.

System for committing execution results when branch conditions coincide

A microprocessor includes a register file that outputs data from multiple registers at one time, and that stores separate data to multiple registers at one time, and an instruction decoder for decoding an instruction to output an operation control signal. The instruction decoder decodes a specific data transfer instruction and outputs a multiple transfer control signal indicating data transfer from multiple registers to multiple registers, a source designating signal for designating multiple source registers, and a destination designating signal for designating destination registers. The register file responds to the source designating signal and outputs data from corresponding registers. The microprocessor further includes an ALU responsive to the control signal for carrying out an operation according to data stored in the register file to provide the result to a register in the register file. The ALU responds to the multiple transfer control signal and provides data read out from the source registers specified according to the source designating signal to the register file. The register file stores data provided from the ALU to the destination registers specified according to the respective destination designating signals. The instruction decoder provides the multiple transfer control signal, and the source and destination designating signals, whereby the ALU directly transfers data in the source registers specified according to the source designating signals to the destination registers specified according to the destination designating signals. Therefore, the transfer operation of a plurality of data can be executed at the same time.

Microprocessor executing multiple register transfer operations with a

Superscalar processor with direct result bypass between execution units

Each of a plurality of buffer memories provided corresponding to a plurality of OUT line fetches a cell through a corresponding address filter and provides the fetched cell to the corresponding OUT line, in normal operation. When any of the buffer memories become full, a spare buffer memory operates in place of the buffer memory, fetches the cell through a corresponding variable buffer memory, and provides the fetched cell to the corresponding OUT line. Such control is effected by a control circuit. Accordingly, in an ATM switch, increase of hardware related to the storage of information and lowering of efficiency in use can be suppressed as much as possible, and the ratio of disposal of the cells can be reduced.

ATM switch

A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing predetermined functions, and a decode state decoding the fetched instructions to issue parallel-processable instructions to related functional units. The decode stage includes a decoder determining whether a branch instruction is included in the received instructions and whether a branch is generated according to the branch instruction. The decoder links a write delaying flag indicating whether the instruction is after a branch instruction and a validity flag indicating whether the instruction is valid to the instruction on issuing the instruction to a functional unit. The functional unit includes an execution stage executing an instruction and a write back stage changing a machine state according to the result of execution in the execution stage. The superscalar-type processor comprises a control circuit forbidding changing of the machine state by a write back stage when a branch is generated according to the branch instruction. The control circuit sets the write back stage in a state of delaying changing of the machine state when it is not yet determined whether a branch is generated according to the branch instruction and executes changing of the machine state with the write back stage when it is determined that no branch is generated according to the branch instruction.

Method and system for invalidating instructions utilizing validity and

Availability flag registers are used for storing flags ia1-ia4 indicating the availability of instructions IR1-IR4 stored in an instruction register. The flags ia1-ia4 are controlled in accordance with misalignment information which represents the degree of an address accessing an instruction cache being shifted from a four word boundary. Upon determining whether or not issuance of an instruction from instruction decoder is possible, it is determined to be unissuable if an availability flag corresponding to each instruction is off. A logic structure for nullifying an instruction stored in an instruction register, when an address in accessing instruction cache 1 is shifted from the four word boundary is implemented without providing the instruction register with a resetting function, and thus a circuit for implementing this logic can be constructed with a reduced number of transistors.

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Hyogo, Japan

Hideki Ando