Matsushita Electric Industrial Co., Ltd.

Hideki Abe

Takahisa Hatano

Kazuhiro Yamada

Yoshikuni Shindo

Kazunari Yamaguchi

Susumu Miura

Kazushige Kida

Noriyuki Iwakura

A decoder includes a first bank and a second bank. The first bank is supplied with dynamic control from a microcomputer via a data bus, and the second bank is supplied with static control data from the data bus via the data bus. The dynamic control data or the static control data is read from an address in the bank designated by an address signal. The dynamic control data read from the first bank and second bank is transferred to one of a plurality of registers designated by the address signal.

Display controller, image display and method for transferring control data

The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency analyzing means for analyzing the frequency of the adjusting signal from the output of the A/D converting means, and dividing ratio setting means for controlling the dividing ratio of the PLL means from the output of the frequency analyzing means, wherein the dot clock is reproduced so that the output of the PLL means may be used as the dot clock signal, thereby realizing a dot clock reproducing apparatus for reproducing automatically the dot clock easily, by setting the dot clock frequency of the video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like.

Dot clock reproducing method and dot clock reproducing apparatus using

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Sapporo, Japan

Hideki Abe