Globalfoundries Inc.

Hidekazu Yoshida

Jongwook Kye

Lei Yuan

Mahbub Rashed

Qi Xiang

Harry Jay Levinson

Juhan Kim

Youngtag Woo

Yunfei Deng

Yuansheng Ma

Paul D Mesa

A process for manufacturing integrated circuit devices includes providing a set of original color rules defining an original color rule space and defining a design space. The improvement involves applying a perturbed color rule space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and reconfiguring the router processing engine in accordance with the exposed decomposition errors.

Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devices

Evaluation of electrical accessibility within a layer of a circuit to pin geometries residing within a cell boundary of the circuit is provided. The evaluating includes, for instance, checking along substantially parallel pin geometry access paths of the layer to determine possible points at which a respective pin geometry of the pin geometries within the cell boundary may be accessed. The evaluating also includes identifying which points of the possible points are accessible access points by any route of the possible routes for electrically connecting to a respective pin geometry of the pin geometries from a first side or a second side of the cell boundary, wherein at least one point of the possible points is identified as not being an accessible access point based on the at least one point being inaccessible by the possible routes.

Evaluation of pin geometry accessibility in a layer of circuit

A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.

Methods for improving double patterning route efficiency

An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Layout designs with via routing structures

Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

Growing community of inventors

San Jose, CA, United States of America

Hidekazu Yoshida