Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Other

Matsushita Electric Industrial Co., Ltd.

Osaka University

Mori, Yusuke

Hidekazu Umeda

Tetsuzo Ueda

Satoshi Tamura

Daisuke Ueda

Yusuke Kinoshita

Fumio Kawamura

Takatomo Sasaki

Kazuhiro Kaibara

Tsuyoshi Tanaka

Isao Kidoguchi

Yasuhiro Yamada

Yasuo Kitaoka

Masahiro Hikita

Hisashi Minemoto

Yusuke Mori

Yasuhito Takahashi

Masashi Yoshimura

Masahiro Ishida

Takashi Ichiryu

Hiroyuki Handa

Yoshiharu Anda

Noboru Negoro

Nanako Hirashita

Yasuhito c/o Matsushita ElIndCoLtd Takahashi

Isao c/o Matsushita ElIndCoLtd Kidoguchi

Fumio c/o Graduate School Of Engineering Kawamura

Hisashi c/o Matsushita ElIndCoLtd Minemoto

Yusuke c/o Graduate School Of Engineering Mori

Yasuo c/o Patsushita ElIndCoLtd Kitaoka

Takatomo c/o Graduate School Of Engineerin Sasaki

A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 &#x3bc;m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by, for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Semiconductor device

A control system includes a control unit. When turning a bidirectional switch element ON, the control unit controls the bidirectional switch element to cause a time lag between a first timing and a second timing. The first timing is a timing when a voltage equal to or higher than a threshold voltage is applied to one gate electrode selected from a first gate electrode and a second gate electrode. The one gate electrode is associated with one source electrode selected from a first source electrode and a second source electrode and having a lower potential than the other source electrode. The second timing is a timing when a voltage equal to or higher than a threshold voltage is applied to the other gate electrode associated with the other source electrode having a higher potential than the one source electrode.

Control system, switch system, power converter, method for controlling bidirectional switch element, and program

A bidirectional switch includes: a first lateral transistor including a first semiconductor layer on the surface of a first conductive layer; a second lateral transistor including a second semiconductor layer on the surface of a second conductive layer; a connection member; a first conductor member; and a second conductor member. The connection member connects the first lateral transistor and the second lateral transistor together in anti-series. The first conductor member electrically connects the first source electrode of the first lateral transistor to the first conductive layer. The second conductor member electrically connects the second source electrode of the second lateral transistor to the second conductive layer.

Bidirectional switch and bidirectional switch device including the switch

A bidirectional switch includes a semiconductor element and a substrate potential stabilizer which stabilizes a substrate potential of a semiconductor element. The substrate potential stabilizer includes a first switch element and a second switch element. Both the first switch element and the second switch element are on when the semiconductor element is on.

Bidirectional switch

A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.

Nitride semiconductor device

A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 &#x3bc;m-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Semiconductor apparatus

A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 &#x3a9;cm or more, and the internal region has a resistivity of 1000 &#x3a9;cm or more.

Nitride semiconductor structure

A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.

Semiconductor device and method of manufacturing the device

A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.

A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

A semiconductor device includes: a substrate, a first nitride semiconductor layerS which includes a plurality of nitride semiconductor layers formed on the substrate, and has a channel region; a second semiconductor layerwhich is formed on the first nitride semiconductor layerS, and has a conductivity type opposite a conductivity type of the channel region; a conductive layer which is in contact with the second semiconductor layer, and includes a metal layeror a high carrier concentration semiconductor layer having a carrier concentration of 1&#xd7;10cmor higher; an insulating layerformed on the conductive layer; a gate electrodeformed on the insulating layer; and a source electrodeand a drain electrodeformed to laterally sandwich the second semiconductor layer

Semiconductor device including separated gate electrode and conductive layer

A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

Field effect transistor and method of manufacturing the same

A semiconductor device includes an undoped GaN layer () formed on a substrate (), an undoped AlGaN layer () formed on the undoped GaN layer () and having a band gap energy larger than that of the undoped GaN layer (), a p-type AlGaN layer () and a high-concentration p-type GaN layer () formed on the undoped AlGaN layer (), and an n-type AlGaN layer () formed on the high-concentration p-type GaN layer (). A gate electrode () which makes ohmic contact with the high-concentration p-type GaN layer () is formed on the high-concentration p-type GaN layer () in a region thereof exposed through an opening () formed in the n-type AlGaN layer ().

Growing community of inventors

Osaka, Japan

Hidekazu Umeda