Central Research Institute of Electric Power Industry

Denso Corporation

Fuji Electric Co., Ltd.

Nuflare Technology, Inc.

Showa Denko K.k.

Toyota Jidosha Kabushiki Kaisha

The Kansai Electric Power Co., Inc.

National Institute of Advanced Industrial Science and Technology

Mitsubishi Electric Corporation

The Kansai Electric Co., Inc.

Central Research Institution of Electrical Power Industry

Hidekazu Tsuchida

Isaho Kamata

Koji Nakayama

Masahiko Ito

Toshiyuki Miyanagi

Yoshitaka Sugawara

Masami Naito

Hiroaki Fujibayashi

Takeshi Tawara

Tomonori Nakamura

Hideki Ito

Koichi Murata

Koichi Nishikawa

Kunihiko Suzuki

Ayumu Adachi

Katsunori Asano

Ryosuke Ishii

Hideyuki Uehigashi

Kazutoshi Kojima

Norihiro Hoshino

Takeshi Okamoto

Liutauras Storasta

Tetsuya Miyazawa

Kazukuni Hara

Yoshiyuki Yonezawa

Keisuke Fukada

Yuichiro Tokuda

Hirofumi Aoki

Katsumi Suzuki

Takahiro Kozawa

Kenji Momose

Naoto Ishibashi

Naohisa Ikeya

Michiya Odawara

Hajime Okumura

Keiichi Matsuzawa

Yuuki Ishida

Akihiro Koyama

Manabu Takei

Shinichiro Miyahara

Hiroyuki Kondo

Shoichi Onda

Shinichiro Matsunaga

Tomohisa Kato

Tomonori Mizushima

Akira Miyasaka

Yasuhiro Ebihara

Takashi Kanemura

Shinji Fujikake

Aki Takigawa

Mitsuru Sometani

Akihiro Otsuki

Kensuke Takenaka

Akira Bando

Shiyang Ji

Toshikazu Sugiura

Toshiro Tsumori

Tae Tawara

Ryohei Tanuma

Tetsuro Hemmi

Masahiro Nagano

Kouichi Murata

Yuji Kiuchi

Takahiro Kanda

A method and an apparatus for manufacturing a silicon carbide single crystal, and a silicon carbide single crystal ingot, obtaining a silicon carbide single crystal reduced in defects such as threading dislocations, are provided. The method manufactures a silicon carbide single crystal by supplying a raw material gas into a reaction vessel with a seed substrate, and heats the interior to grow a silicon carbide single crystal on the surface of the seed substrate. The method includes growing the silicon carbide single crystal on the seed substrate surface, while controlling the temperature, to perform pair annihilation of threading dislocations or synthesis of the threading dislocations; and a second step of maintaining the temperature inside the reaction vessel in the state of the first predetermined temperature after execution of the first step, to bring the leading ends of the threading dislocations close to the surface of the seed substrate.

Method and apparatus for manufacturing silicon carbide single crystal, and silicon carbide single crystal ingot

In a silicon carbide single crystal wafer, a dislocation density contained therein is 3500 dislocations/cmor less, and a difference of the dislocation density among a wafer central part, a wafer peripheral part and a wafer intermediate part is less than 50% of an average value thereof.

Silicon carbide single crystal wafer, and methods for manufacturing silicon carbide single crystal ingot and the silicon carbide single crystal wafer

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×10/cm.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A raw material gas is supplied to a space in which a silicon carbide seed crystal is placed. A silicon carbide single crystal is grown on the seed crystal by keeping a monosilane partial pressure at 4 kPa or more and heating the space to a temperature of 2400° C. to 2700° C. The temperature of the space and supply of the raw material gas are controlled such that a temperature gradient of a growth crystal surface of the silicon carbide single crystal in a radial direction is 0.1° C./mm or less, and a radius of curvature of the growth crystal surface is 4.5 m or more, thereby producing a silicon carbide single crystal ingot having a growth length of 3 mm or more and an internal stress of 10 MPa or less. The ingot is then cut into a silicon carbide single crystal wafer.

Methods for manufacturing silicon carbide single crystal ingot and silicon carbide single crystal wafer

A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films. A lifetime of the minority carrier of the first semiconductor region is shorter than that of the rest of the second first-conductivity-type epitaxial layer.

Vertical MOSFET having trench gate structure containing silicon carbide

A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.

Semiconductor wafer evaluation apparatus and semiconductor wafer manufacturing method

A silicon carbide single crystal contains a heavy metal element having a specific gravity higher than a specific gravity of iron. An addition density of the heavy metal element at least in an outer peripheral portion of the silicon carbide single crystal is set to 1×10cmor more.

Silicon carbide single crystal

A SiC epitaxial wafer according to an embodiment includes: a SiC substrate; and a SiC epitaxial layer formed on a first surface of the SiC substrate. The in-plane uniformity of a density of Zcenters of the SiC epitaxial layer is 5% or less.

SiC epitaxial wafer and method for producing SiC epitaxial wafer

A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Semiconductor device and method of manufacturing semiconductor device

A method for producing a SiC epitaxial wafer according to the present embodiment includes: an epitaxial growth step of growing the epitaxial layer on the SiC single crystal substrate by feeding an Si-based raw material gas, a C-based raw material gas, and a gas including a Cl element to a surface of a SiC single crystal substrate, in which the epitaxial growth step is performed under growth conditions that a film deposition pressure is 30 torr or less, a Cl/Si ratio is in a range of 8 to 12, a C/Si ratio is in a range of 0.8 to 1.2, and a growth rate is 50 &#x3bc;m/h or more from an initial growth stage.

SiC epitaxial wafer and method for producing same

A supply part includes a first partition, a second partition under the first partition, a third partition under the second partition, a first flow path between the first partition and the second partition allowing a first gas to be introduced therein, a second flow path between the second partition and the third partition allowing a second gas to be introduced therein, a first piping extending from the second partition to reach below the third partition and being communicated with the first flow path, a second piping extending from the third partition to reach below the third partition and being communicated with the second flow path, and a convex portion provided on an outer circumferential surface of the first piping or an inner circumferential surface of the second piping protruding from one of the outer circumferential surface and the inner circumferential surface toward the other one.

Film forming apparatus

During epitaxial growth of an n-type drift layer having a uniform nitrogen concentration, vanadium is doped in addition to the nitrogen, whereby an n-type lifetime reduced layer is selectively formed in the n-type drift layer. The n-type lifetime reduced layer is disposed at a depth that is more than 5 &#x3bc;m from a pn junction surface between a p-type anode layer and the n-type drift layer in a direction toward a cathode side, and the n-type lifetime reduced layer is disposed separated from the pn junction surface. Further, the n-type lifetime reduced layer is disposed in a range from the pn junction surface to a depth that is &#x2153; times a thickness of the n-type drift layer. A vanadium concentration of the n-type lifetime reduced layer is 1/100 to &#x2155; of a nitrogen concentration of the n-type lifetime reduced layer.

Silicon carbide semiconductor device and a method of manufacturing the silicon carbide semiconductor device

An n-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n-type epitaxial layer decreases and the n-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.

Silicon carbide semiconductor substrate, method of manufacturing a silicon carbide semiconductor device, and silicon carbide semiconductor device

On a front surface of an n-type starting substrate containing silicon carbide, a pin diode is configured having silicon carbide layers constituting an n-type buffer layer, an n-type drift layer, and a p-type anode layer sequentially formed by epitaxial growth. The n-type buffer layer is formed by so-called co-doping of nitrogen and vanadium, which forms a recombination center, together with an n-type impurity. The n-type buffer layer includes a first part disposed at a side of a second interface of the buffer layer with the substrate and a second part disposed at side of a first interface of the buffer layer with the drift layer. The vanadium concentration in the second part is lower than that in the first part. The vanadium concentration in the second part is at most one tenth of the maximum value Vmax of the vanadium concentration in the n-type buffer layer.

A film forming apparatus according to an embodiment of the invention includes: a film forming chamber configured to form a film on a substrate; a susceptor configured to place the substrate thereon; a rotating part configured to rotate the susceptor; a heater configured to heat the substrate; and a gas supplier configured to supply process gases into the film forming chamber, wherein the susceptor includes: a ring-shaped outer circumferential susceptor supported by the rotating part; a holder provided at an inner circumferential portion of the outer circumferential susceptor, the holder configured to hold the substrate; a ring-shaped plate provided over the outer circumferential susceptor; and a cover member configured to cover a top surface and an outer circumferential surface of the plate and an outer circumferential surface of the outer circumferential susceptor.

Film forming apparatus, susceptor, and film forming method

Growing community of inventors

Yokosuka, Japan

Hidekazu Tsuchida