Sharp Kabushiki Kaisha Corporation

Nintendo Co., Ltd.

Sharp Kabushika Kaisha

Sharp Kabushiki K.k.

Hidekazu Takata

Ken Sumitani

David Novosel

Thomas Mnich

Yuji Tanaka

Hidehiko Tanaka

Yasuo Miyamoto

Kengo Maeda

Yasumichi Mori

Kazuya Fujita

Haruyasu Fukui

Kazutomo Shioyama

Yoshitaka Okita

Hiroshi Kiso

Yasuyuki Aikawa

Masato Imanishi

Masahiro Takata

A display element and electronic element module according to the present invention is described, in which a lens is formed as part of a translucent support substrate having a display disposed thereon, the lens being formed on a part other than where the display is disposed, where an electronic element is disposed for the lens.

Display element having a lens being formed as part of a translucent support substrate having a display disposed thereon

A semiconductor storage device includes a program ROM and a flash memory, and the program ROM includes a program data storing area and a dummy data storing area, and the flash memory includes a program data storing area and a dummy address storing area. An address comparison circuit compares an input address and a dummy address being stored in the dummy address storing area with each other. An output inhibiting circuit allows to read program data from the program ROM when the both addresses are not coincident with each other, and inhibits the program data from being read at a time of incoincidence. In a case of the incoincidence, an address conversion circuit produces a read address of the flash memory, whereby the program data is read from the flash memory.

Security system method and apparatus for preventing application program unauthorized use

A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.

Semiconductor storage device, control device, and electronic apparatus

A semiconductor memory device of the present invention includes: a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.

Semiconductor memory device, method for controlling same, and electronic information apparatus

A semiconductor device includes: a read-only semiconductor memory device; and a nonvolatile semiconductor memory device for replacing defective data in at least one defective region which occurred in the read-only semiconductor memory device with modification data for modifying the defective data, the nonvolatile semiconductor memory device including: a memory section capable of electrically writing address data indicating an address of the defective region, and the modification data; and an address determination circuit for outputting a determination result signal which inactivates the read-only semiconductor memory device when the address data matches an address provided from outside the semiconductor memory device, wherein the nonvolatile semiconductor memory device reads and outputs the modification data from the memory section when the address data matches the address.

Semiconductor memory device

A reset device detects a rise of a supply voltage to start outputting a reset signal. The reset device includes a voltage detection circuit for detecting the supply voltage. The voltage detection circuit includes a ferroelectric capacitance element for detecting the supply voltage.

Reset apparatus, semiconductor IC apparatus, and semiconductor memory apparatus

A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

Semiconductor storage device

A semiconductor device includes: a memory having a memory space for recording data, the memory space including addresses; at least one first storage section for storing at least a portion of an address at which access to the memory space is requested and/or data which is requested to be written to the memory space; and an operation restriction circuit for at least partially restricting operations to be performed on the memory. The operation restriction circuit controls restriction on the operations to be performed on the memory based on at least a portion of the data and/or the address stored in the at least one first storage section.

Semiconductor device and control device for use therewith

A nonvolatile semiconductor memory device includes a plurality of memory cell array blocks including a first memory cell array block to which a data write operation is performed or from which a data erasure operation is performed, and a second memory cell array block from which a data read operation is performed concurrently with the data write operation or the data erasure operation to or from the first memory cell array block; and a plurality of block lock setting devices respectively provided in correspondence with the plurality of memory cell array blocks for placing the second memory cell array block into a locked state in which a data write operation to and a data erasure operation from the second memory cell array block is prohibited.

Nonvolatile semiconductor memory device with concurrent memory access and data locking

A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.

Semiconductor memory device and restoration method therefor

A semiconductor memory device includes a plurality of memory banks each including a plurality of memory cells, one of which is selectable in accordance with an address signal; a memory bit line for receiving a read voltage from the selected memory cell; a reference cell for outputting a reference voltage; a reference bit line for receiving the reference voltage; a comparison and amplification device for amplifying a difference between a voltage from the memory bit line and a voltage from the reference bit line; and a load capacitance adjusting device for providing a third load capacitance to the reference bit line so that a first load capacitance between the selected memory cell and the comparison and amplification device is substantially equal to a second load capacitance between the reference cell and the comparison and amplification device.

A switching transistor is provided which applies predetermined voltage to a plurality of word lines based on a predetermined signal from a power on reset circuit, until predetermined potential becomes stable, when the predetermined potential is applied to the bit line or to the plate line, such as at the time of power on, to connect the bit line connected to each memory cell and the memory cell capacitor, as well as applies a control signal to the gate to thereby electrically connect the bit line and the plate line.

Semiconductor memory device having a ferroelectric memory capacitor

A semiconductor memory device includes a plurality of memory arrays including a plurality of memory cells; a plurality of fuses having one of a disconnected state and a connected state for classifying the plurality of memory arrays into a plurality of banks; and a selection circuit for selecting one of the plurality of banks based on the state of the plurality of the fuses and an address signal.

Semiconductor memory device and method for producing the same

The semiconductor memory device of this invention includes a capacitor, a first transistor, and a second transistor, wherein the capacitor includes a first electrode, a second electrode opposing the first electrode, and a ferroelectric film sandwiched by the first and second electrodes, and stores and holds binary information utilizing a polarizing state of the ferroelectric film, the first transistor includes a first electrode, a second electrode, and a gate electrode, the second electrode being connected to the first electrode of the capacitor, and the second transistor includes a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the second electrode of the capacitor.

Semiconductor memory device utilizing a polarization state of a

A non-volatile semiconductor memory device according to the present invention includes: a memory cell including a capacitor having a ferroelectric film interposed between and a first electrode and a second electrode, the capacitor being capable of retaining binary information responsive to the ferroelectric film taking one of first and second polarization states, and a transistor having a source, a drain, and a gate, the source being coupled to the first electrode of the capacitor; a word line coupled to the gate of the transistor; a bit line coupled to the drain of the transistor; a plate line coupled to the second electrode of the capacitor; and a sense amplifier coupled to the bit line. When performing a read operation for the memory cell, a voltage on the bit line is amplified to a supply voltage by the sense amplifier if the ferroelectric film is in the first polarization state; and the voltage on the bit line is amplified to a negative voltage by the sense amplifier if the ferroelectric film is in the second polarization state.

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Nara, Japan

Hidekazu Takata