Kabushiki Kaisha Toshiba

Toshiba Infrastructure Systems & Solutions Corporation

Hidekazu Saito

Takufumi Yoshida

Shizu Sakakibara

Shigeta Kuninobu

Takuma Akagi

Kenjiro Kanayama

Tsukasa Miyawaki

Ayumi Ishii

Masaki Kume

Eiji Hasegawa

Naoki Taniguchi

Koji Ehara

Yoshikatu Hatagaki

According to one embodiment, an information processing apparatus according to an embodiment includes an extractorconfigured to extract a representative point that appears at a rate higher than or equal to a predetermined appearance rate, based on a point included in package historical data recorded when a package is delivered and a delivery plan creatorconfigured to create a first delivery plan with respect to the representative point.

Information processing apparatus, information processing system, information processing method, information processing program, and display device

According to an embodiment of the present invention, a probability to achieve a purpose is increased in a case where information is intermittently allocated to a plurality of elements. An information processing apparatus according to an embodiment of the present invention is an information processing apparatus that allocates information to respective elements included in a first set and includes an allocator. The allocator uses a first subset and a second subset, and allocates the information to at least one element included in the first subset. The first subset is constituted by elements which are included in the first set and in which information allocation may be performed at a present time. The second subset is constituted by elements which are included in the first set and in which the information allocation is not performed at the present time.

Information processing apparatus, information processing method, and information processing system

There are provided a semiconductor device and a function module test method, capable of reducing the test time of function modules and reducing the number of test pins. This semiconductor device is formed so as to make test inputs and test outputs of a plurality of function modules having the same function respectively common, conduct tests on arbitrarily selected function modules simultaneously in parallel, and give a pass/fail decision on the semiconductor device including the function modules on the basis of results of comparison between a test result of arbitrary one function module and test results of other function modules.

Circuit, semiconductor device and method for enhancing test efficiency of function modules

An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Clock generator in which external oscillator is disabled after internal

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Katsushika, Japan

Hidekazu Saito