Canon Kabushiki Kaisha

Hideho Inagawa

Shigenobu Nojo

Seiji Hayashi

Toru Otaki

Daishiro Sekijima

Toru Osaka

Yasushi Takeuchi

Hiroyuki Yamaguchi

Yoshimi Terayama

Masafumi Kamei

Tohru Ohsaka

Tsunao Hombo

Tomoyasu Arakawa

Makoto Takayama

Shinichi Nishimura

Tatsuo Nishino

Satoshi Sugimoto

Shin'ichi Nishimura

Shin′ichi Nishimura

A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Multilayered printed circuit board

A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.

Integrated circuit having wide power lines

A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.

Chip with power and signal pads connected to power and signal lines on substrate

A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.

Digital electronic apparatus with suppressed radiant noise

Semiconductor integrated circuit device

A cable arranging structure for exchanging electric signals between a pair of printed circuit boards includes at least a pair of electrically conductive members adapted to arrange the cable between them over the entire length thereof. The electrically conductive members show an electric potential substantially equal to that of the ground. Such a structure requires only the two electrically conductive members to be rigidly secured so that radiant noises generated by the cable can be effectively suppressed by means of the structure without the need of deforming the cable.

Cable arranging structure

This invention is directed to provide a shielded cable connector that can stabilize electrical connection between a cable-side shield member and a board-side ground pattern. In order to achieve this object, a shielded cable connector to be mounted on a shielded cable having a signal transmission line and a shield member around it includes a metal outer shell member to come into direct contact with the shield member. The outer shell member includes a contact portion extended to come into direct contact with a ground pattern of an electric board to which the shielded cable is to be connected.

Shielded cable connector and electronic device

A shielded cable with a connector, in which the connector is connected to an end portion of the shielded cable formed by covering a plurality of cores with a shielding member, comprises an electrode portion provided with a plurality of electrodes connected to the cores, a conductive inner housing having a fitting portion for fitting to a connector which is to be fitted to the connector, and having the electrode portion therein, and a conductive outer housing which is used in combination with the inner housing and contains cores exposed from the shielded cable, wherein the outer housing is electrically connected to the shielding member, and the outer housing is electrically connected to the inner housing through a conductive connecting portion electrically connected to the fitting portion of the inner housing.

Shielded cable with connector

A printed wiring board having assembled thereon a grid array type package, a multi-terminal device with many terminals arranged in matrix, is provided, through first signal connection holes, signal lines, and second connection holes, with many numbers of lands divided into plural blocks, being arranged in matrix on a first layer to connect each terminal of the multi-terminal device correspondingly, signal line patterns connected with many lands, and drawn out in the same direction per block, and first signal patterns from lands positioned on the innermost line of many lands. Then, the wiring patterns of the signal lines are drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it easier for the printed wiring board to effectuate wiring connections without making them complicated or increasing the number of layers of the printed wiring board. Also, with the provision of ground patterns that surround signal lines, it is made possible to reduce unwanted radiant, as well as to suppress the occurrence of malfunctions of electronic equipment due to reflections and ground bounces.

Printed-wiring board

Noise frequency generated from a circuit is determined. The distance between two arbitrary lines of a plurality of power feed lines or a plurality of power return lines extending parallel to each other is determined on the basis of the determined noise frequency in question. The distance between jumper lines for bridging the two arbitrary lines is determined on the basis of the noise frequency, thereby suppressing emitted noise which can be generated on a printed circuit board.

Printed circuit board with noise suppression

A circuit board having a printed capacitor whose capacitance is easily adjusted includes a plurality of through-holes arranged in arrays and electrically connected to each other via conductive films. Therefore, first and second electrode portions are arranged to oppose each other, and form a printed capacitor. The capacitance of the capacitor can be adjusted by the number and diameter of through-holes, and the interval between each two adjacent through-holes. Therefore, even when a large-capacitance capacitor is to be formed, the printed capacitor can be rendered compact.

Printed circuit board having an embedded capacitor

A printed circuit board capable of suppressing radiation noise efficiently includes a first conductive layer where a plurality of power lines are provided at predetermined spacing along one direction, a second conductive layer where a plurality of power lines are provided at predetermined spacing along a direction orthogonal to the one direction, and a plurality of plated through holes for connecting the power lines on the first conductive layer and the power lines on the second conductive layer at the overlapping points of those lines. The power lines contain thin lines and thick lines spaced between a plurality of the thin lines. The predetermined spacing is determined based on a rising time or falling time of the output signal of the IC to be mounted on the circuit board.

Growing community of inventors

Yokohama, Japan

Hideho Inagawa