Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki

Hidehiko Tanaka

Katsuyuki Machino

Masahiro Ise

Toshiyuki Matsubara

Teiji Terasaka

Hidekazu Takata

Takaaki Okamoto

Yasumichi Mori

Shinsuke Anzai

Tatsuya Kimura

Hasahiro Ise

Masahiko Ise

Katsuyuki Machimno

A flash memory constructed of a plurality of memory cells M, . . . , Mselected by the outputs of an X-decoderand a Y-decoderfor generating a row address and a column address is provided with a measurement use write pulse generator circuitwhich simultaneously supplies write signals of different pulse widths to the memory cells on an identical column, and a select circuitwhich switches over so as to supply the write signals from the measurement use write pulse generator circuitto the word lines M, . . . , Mon the identical column during pulse width measurement and supply the word line signal from the X-decoderto the corresponding one word line WLduring normal access. According to this flash memory, the total write time can be reduced by reducing the frequency of repetition of write and verify.

Nonvolatile semiconductor storage device and write time determining method therefor

A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.

Semiconductor memory device

A non-volatile semiconductor memory device is provided, which comprises a memory array comprising memory cells, in which each memory cell is capable of storing data values depending on the voltages thereof, the data values include a first data value corresponding to a first voltage range and a second data value corresponding to a second voltage range, and the first data is written in a memory cell of the memory cells, a determination section for determining whether a voltage value of the memory cell is higher or lower than a reference value set between a maximum value and a minimum value of the first voltage range, and a rewrite section for rewriting the first data into the memory cell based on a determination result of the determination section so that a margin between the first voltage range and the second voltage range in the memory cell is enlarged.

Non-volatile semiconductor memory device and rewriting method

The present invention is to provide a method for designating a memory bank to be refreshed efficiently and a start and termination procedure of a self-refresh. In a dynamic RAM including a plurality of memory banks,A,,B, memory access actions being allowed to be independently on the respective memory banks, and a refresh control circuit for allowing the plurality of memory banks,A,,B to be refreshed in a lump and for allowing one memory bank,A or,B of the plurality of memory banks designated to be refreshed, a semiconductor memory device is configured such that when a row address input terminal or one of specific input terminals other than the row address input terminal is at a high level, the plurality of memory banks are refreshed in a lump; and when the row address input terminal or one of specific input terminals other than the row address input terminal is at a low level, one of the plurality of memory banks is designated to be refreshed in accordance with a bank selecting bit composed of one bit or a combination of a plurality of bits of row addresses other than the row address.

In a ferroelectric memory, a plate line and a complementary bit line are electrically connected with each other by a MOS transistor turned on, so that a voltage of the complementary bit line amplified by a sense amplifier is transferred to the plate line. An electric current for driving the plate line flows only when the voltage of the complementary bit line is different from that of the plate line. Because the sense amplifier can drive the plate line, it is unnecessary to provide the ferroelectric memory with a plate line-driving circuit.

Ferroelectric memory

In a semiconductor memory device of the present invention, a read operation is performed by activating a first word line of the plurality of word lines, transferring data read out from the memory cells simultaneously selected by the first word line via the plurality of bit line groups, latching the data from the plurality of bit line groups in the plurality of first sense amplifiers via the first switch section, transferring data from one of the plurality of first sense amplifiers to the first common data line via one of the plurality of third switch sections, and outputting the data from the first common data line to an external unit. A refresh operation is performed, simultaneously with the read operation, by activating a second word line of the plurality of word lines, and refreshing data read out from the memory cells simultaneously selected by the second word line using the plurality of second sense amplifiers via the second switch section.

A semiconductor memory device having: a pair of bit signal lines; a sense amplifier disposed between the pair of bit signal lines; a ground potential side transistor inserted between the sense amplifier and a ground potential; and a power supply potential side transistor circuit inserted between the sense amplifier and a power supply potential network. When the ground potential side transistor is turned ON, one of the pair of bit signal lines which is closer to the ground potential is pulled into the ground potential via the sense amplifier, and when the power supply potential side transistor circuit is turned ON, the other one of the pair of bit signal lines which is closer to the power supply potential is pulled into the power supply potential via the sense amplifier, thereby amplifying a potential difference between the pair of bit signal lines.

Semiconductor memory device operating at a low level power supply voltage

A 16 Mbit DRAM of the invention is made up of a nexus of four 4 Mbit DRAM chips which are formed adjacent to one another on the wafer and each constitute an individual 4 Mbit DRAM, the connection between the 4 Mbit DRAMs is formed through a short-circuit protecting circuit provided within each 4 Mbit DRAM and an interconnection/controller circuit portion formed in the dicing area between the 4 Mbit DRAMs. When the nexus is cut along the dicing area containing the interconnection/controller circuit portion, 4 Mbit DRAM chips and/or 8 Mbit DRAM chips can be produced as desired.

Semiconductor integrated circuit device having a short circuit

A semiconductor memory device includes: a plurality of word lines; a plurality of drive lines; a word line driving section for activating one of the plurality of word lines in accordance with a row address; a column selection section for, in accordance with a column address, selecting one of a plurality of ferroelectric memory cells coupled to the activated word line; a plate driving signal application section for applying a plate driving signal to at least a selected one of the plurality of drive lines, the at least one selected drive line being associated with the activated word line; and a switching section for coupling or detaching the plurality of ferroelectric memory cells to or from the at least one selected drive line. The column selection section controls the switching section so that only the selected ferroelectric memory cell is coupled to the at least one selected drive line.

A semiconductor memory device includes at least two memory cells included in a first bank; at least two word lines; and a first sensing amplifier and a second sensing amplifier. The first sensing amplifier amplifies and holds data of one of the memory cells connected to one of the word lines. The second sensing amplifier amplifies and holds data of one other memory cell connected to one other word line.

Semiconductor memory device and method for controlling the same

A semiconductor memory device of the present invention includes a memory cell array including m sub-arrays, each having a number of memory cells arranged in a matrix and including M/m (m is an integer of 2 or more; M/m is an integer of 2 or more) memory rows and N (N is an integer of 2 or more) memory columns. In an image space in a matrix including M pixel rows and N pixel columns, the M pixel rows are divided into M/m blocks, m pixel rows in each of the M/m blocks are in a one-to-one correspondence with the m sub-arrays, and the M/m blocks are in a one-to-one correspondence with the M/m memory rows in each of the sub-arrays. The semiconductor memory device also includes a row address control circuit for, in a case where a pixel address of data on the image space is input, accessing the memory cell array by selecting a memory row corresponding to a block to which the data belongs in a sub-array corresponding to a pixel row of the block to which the data belongs.

Semiconductor memory device for temporarily storing digital image data

A non-volatile semiconductor memory device includes a plurality of memory cells each including a capacitor as a memory element, the capacitor sandwiching a ferroelectric member. The non-volatile semiconductor memory device further includes: a first counter for counting the number of write accesses and read accesses for writing or reading first logic data to each one of the plurality of memory cells; a second counter for counting the number of write accesses and read accesses for writing or reading second logic data to the memory cell; and a refresh control circuit for performing, when either a first value counted by the first counter or a second value counted by the second counter exceeds a predetermined value, a refresh operation by applying electric fields for causing a polarization state of the ferroelectric member of the capacitor to make a complete round on a hysteresis curve of the ferroelectric member in a corresponding one of the plurality of memory cells for which the first or second value counted by the first counter or the second counter has exceeded the predetermined value.

Non-volatile semiconductor memory device

A very useful data transmission system having a plurality of transmission modules connected to a single cable in a multidrop manner is disclosed herein. The system features its ability to check the transmission state at the level of individual modules through use of a proper code notation (typically, Manchester code). The system detects a specific module with proper signals lasting at the same level for more than a given time, except cable outputs, and treats it as involving a faulty condition and compels the transmission state to a halt, thus preventing only the faulty module or modules from transmitting signals thereby avoiding breakdown of the whole system.

Data transmission system

A signal transmission system over building or house wiring includes noise reduction circuit to reduce noise including asynchronous noise and synchronous noise. Received pulses are sampled in a given interval and the number of continous pulses in question during the sampling interval is counted. The pulses in question are ignored as noise if the number of pulse counting is less than a predetermined reference count and the pulses are treated as true signals if the number is more than said reference count.

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Nara, Japan

Hidehiko Tanaka