National Semiconductor Corporation

Hidehiko Suzuki

Hidenori Kobayashi

Nicky Miles Johnson

Kenji Tomiyoshi

Barry James Culpepper

John Patrick Fairbanks

A system and method is disclosed for minimizing power consumption in a reference voltage circuit. A capacitor is coupled to a reference voltage circuit and charged to a voltage that equals the reference voltage of the reference voltage circuit. The capacitor is then decoupled from the reference voltage circuit and power to the reference voltage circuit is turned off. The capacitor then provides the capacitor voltage to other circuits as a reference voltage. After a selected period of time has elapsed since the capacitor was last charged to the reference voltage, the reference voltage circuit is turned on and the capacitor is again coupled to the reference voltage circuit. The reference voltage circuit then recharges the capacitor to the reference voltage level. This process is repeated to periodically charge the capacitor to the reference voltage.

Minimizing power consumption of a reference voltage circuit using a capacitor

A circuit for improving transient response for a load coupled to a voltage regulator by employing both load current level information and the regulator's output voltage to control a loop that provides relatively faster and accurate regulation of the regulator's output voltage. The circuit includes an error amplifier that is coupled to a reference voltage and feedback resistors connected to the regulator's output voltage. This error amplifier outputs a compensation signal that is subsequently summed at a summing point with additional information regarding the amount of current flowing through the load. Then, this summed compensation signal is subsequently employed by a pulse width modulation (PWM) comparator and other components to regulate the regulator's output voltage with improved speed and accuracy. The circuit can be arranged in different topologies, including buck, boost, and buck/boost.

Transient load response for a voltage regulator with a load current based control loop

System and method for minimizing power consumption of a reference voltage circuit

A boost converter with a flying capacitor topology is provided. The flying capacitor is charged during a first half of a cycle. During a second half of the cycle, the output voltage of the boost converter is supplied from Vdd until the output voltage approximately reaches Vdd. At that point, the flying capacitor is used to provide the output voltage.

Apparatus and method for a boot strap circuit for a boost voltage converter

A timer circuit is arranged for reduced propagation delay and improved stability at low supply voltages. The timer circuit includes a capacitor circuit, a voltage offset circuit, an inverter circuit, and a current source circuit. The current source circuit is arranged to provide a current. Also, the capacitor circuit is arranged to provide a voltage ramp in response to the current. The voltage offset circuit is configured to provide a voltage offset. Further, the current source circuit, the capacitor circuit, and the voltage offset current are arranged to provide two voltage ramps that are offset from each other. Additionally, the inverter circuit includes a p-type transistor and an n-type transistor. The p-type transistor is configured to receive one of the two voltage ramps, and the n-type transistor is configured to receive the other of the two voltage ramps.

Apparatus and method for reducing propagation delay

Quiescent currents in a circuit that includes a regulator are reduced by disabling selected portions of the circuit. A window comparator is selected activated to evaluate the input voltage such that a first operating mode is activated when the input voltage is within a predetermined voltage range and a second operating mode is activated when the input voltage is outside of the predetermined voltage range. The battery voltage is used a reference signal when the first mode is selected such that a voltage reference circuit can be disabled to reduce power, while the voltage reference circuit is enabled when the second mode is selected. Another comparator circuit is periodically activated to compare the reference signal to the output voltage. The regulator is disabled after the output voltage exceeds a first level. The output voltage collapses below a second level associated, the evaluation and regulation process is repeated.

Voltage regulator power management apparatus

A switching DC-to-DC converter having at least one power channel including an inductor and a controller which generates at least one power switch control signal for at least one power switch of each power channel. The converter is configured to operate in a continuous mode when the inductor current remains above zero, to enter a discontinuous pulse skipping mode of operation when the inductor current falls to zero (which occurs when the load current is below a threshold value), and to leave the discontinuous pulse skipping mode and resume continuous mode operation when the inductor current rises above zero. The main difference between the continuous and discontinuous pulse skipping modes is that in the continuous mode, a power switch has a duty cycle determined by a feedback signal indicative of the converter's output potential V (so that the duty cycle is independent of the current drawn from the converter by the load), and in the discontinuous pulse skipping mode the power switch has a duty cycle which is the longer of a minimum duty cycle and a discontinuous (non-pulse-skipping) mode duty cycle. The discontinuous pulse skipping mode is more efficient than the continuous mode under conditions of low load current. Preferably, the controller includes cycle-skipping circuitry operable in the discontinuous pulse skipping mode and optionally also the continuous mode to cause the power switch to remain off for at least one cycle under the condition that the converter's output potential rises above a threshold. Preferably, the cycle-skipping circuitry includes a comparator which compares an error amplifier output (indicative of the converter output potential) with a threshold potential, and logic circuitry (e.g., an AND gate coupled to the comparator output) which asserts a latch-clearing signal once per switching cycle when the comparator output indicates that the converter's output has risen above the threshold. Other aspects of the invention are a switching controller for use in such a converter and a method for generating power switch control signals for such a converter in a discontinuous pulse skipping mode of operation.

Switching DC-to-DC converter with discontinuous pulse skipping and continuous operating modes without external sense resistor

An on-time signal generation circuit for use in a switching DC-to-DC converter, a switching DC-to-DC converter including such a circuit, and a method for generating an on-time signal which is a binary pulse train comprising pulses T,, where the width of each pulse T,is equal to T,(V,/V,), where T,, V,, and V,are, respectively, the switching period and the input potential of a DC-to-DC converter, and a control potential. The control potential V,is one of the output potential of the DC-to-DC converter and a DC potential proportional to a desired level of such output potential. The on-time signal generation circuit includes a comparator, a ramp generator with an output coupled to one input of the comparator, and an amplifier with an output coupled to the other input of the comparator. The ramp generator generates a periodic ramped potential having peak level kV,and period T,. The amplifier receives the control potential V,, and is configured to assert an amplified potential kV,in response thereto. In response to potential kV,from the amplifier and ramped voltage kV,from the ramp generator, the comparator asserts a pulse train comprising pulses T,. The width of each pulse T,is equal to T,(V,/V,), and thus is indicative of the nominal or critical power switch on-time needed for the DC-to-DC converter to produce an output equal to V,in response to input V,. Preferably, the on-time signal generation circuit is implemented so that the width of each pulse T,is equal to T,(V,/V,) independently of process variations and variations in operating temperature.

Switching DC-to-Dc converter having on-time signal generation circuit and method for generating signal indicative of converter on-time

A switching voltage regulator is stabilized against changes in input voltage by suppressing the increase in loop gain due to increased input voltage. The reduction of loop gain is achieved by use of a modified triangle waveform which is compared to an error signal to switch the regulator output stage.

Growing community of inventors

Tokyo, Japan

Hidehiko Suzuki