Fujitsu Corporation

Hidehiko Nishida

Akira Hattori

Minoru Koshino

Masanori Takahashi

Hiroshi Komatsuda

Terutaka Tateishi

A request cancel system is incorporated in a processing system which includes a main storage unit having a plurality of banks, a memory control unit and a plurality of access units, such as central processing units (CPUs), which access the banks of the main storage unit via the memory control unit. A check part in the request cancel system detects whether or not a bank designated by an address of an access request from one of the access units is in use by reading a corresponding bank busy flag from a bank busy flag group. After the check part has determined that a bank designated by an address of a first access request is not busy, a flag is sent to the bank busy flag group to indicate that the bank accessed by the first access request is busy. A second access request to the bank accessed by the first access request can be processed by the check part before the flag is set in the bank busy flag group. A comparator compares the addresses of the first access and second access requests and outputs a coincidence signal when the addresses of the first and second access requests coincide. A request cancel controller cancels the second access request in response to the coincidence signal from the comparator.

Request cancel system for cancelling a second access request having the

In a data processing system including a plurality of multi-processor systems, each multi-processor system having at least one central processing unit and at least one main memory both connected to a memory control unit, each memory control unit is connected to each other memory control unit, the memory control unit comprises plural ports, plural registers, access selection circuits for innner and outer access, a priority control circuit, a first and a second control circuit, and wait signal reset circuit, a priority of accesses from the same central processing unit to the other multi-processor system is detected, and the registers to store the access request signals in the other multi-processor system are efficiently used by adding a priority control signal to the access request signal. Thus, the data throughput of the system and the speed of the access are improved.

Data processing system with memory-access priority control

The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.

Access request control apparatus which reassigns higher priority to

A data processor system includes a plurality of multiprocessor systems, and each multiprocessor system is connected through each memory control unit of each multiprocessor system. Each multiprocessor system comprises a memory control unit, at least one central processing unit, at least one channel control unit, and at least one main memory unit. The central processing unit, channel control unit, and main memory unit are connected to the memory control unit via interface lines. The memory control unit comprises at least two pipelines and at least two access requests to the main memory unit belonging to the pipe-line, and the other pipe-line is used for access requests to another main memory unit belonging to another memory control unit.

Data processor system having improved data throughput in a

This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access requesting unit in parallel with the access to MS by the first access request.

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Tokyo, Japan

Hidehiko Nishida