Semiconductor Energy Laboratory Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Other

Hidehiko Chimura

Jun Koyama

Yasushi Kubota

Kenichi Katoh

Shunpei Yamazaki

Yukio Tanaka

Yasukuni Yamane

In an active matrix panel, a pixel matrix which includes a plurality of gate lines, a plurality of source lines, and thin film transistors is formed on a first transparent substrate. A second transparent substrate is formed opposite to the first transparent substrate. A liquid crystal material is disposed between the first and second transparent substrates. A gate line driver circuit and a source line driver circuit are formed by a P-type, an N-type, a complementary type thin film transistors (including silicon film) or the like on the first transparent substrate. Also, a data processing circuit for performing mask processing or the like is formed by the thin film transistors or the like on the first transparent substrate.

Active matrix panel

In an active matrix panel, a pixel matrix which includes a plurality of gate lines, a plurality of source lines, and thin film transistors is formed on a first transparent substrate. A second transparent substrate is formed opposite to the first transparent substrate. A liquid crystal material is disposed between the first and second transparent substrates. A gate line driver circuit and a source line driver circuit are formed by a P-type, an N-type, or a complementary type thin film transistors (including silicon film) on the first transparent substrate. Also, a data processing circuit for performing mask processing is formed by the thin film transistors on the first transparent substrate.

An active matrix display device has a number of pixels arranged in matrix form, signal lines for supplying display signals to the pixels, and a driver circuit for driving the signal lines. The driver circuit includes a frequency divider circuit for frequency-dividing input multi-phase clock signals, a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals, and a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.

Active matrix display device and scanning circuit

A plurality of partial image display portions are provided. Each of the partial image display portions is formed by at least one signal line driver circuits and at least one of scanning line driver circuits. Each partial image display portion displays a part of one frame of image. The whole one frame of image is displayed by all of the partial image display portions.

Active matrix display and image forming system

Active matrix display and image forming system based on multiple partial image displays

An active matrix liquid crystal display consuming only a small amount of electric power. The liquid crystal display has two driver circuits which drive two sets of signal lines, respectively, One set of signal lines creates the upper half of a frame of image displayed on the viewing screen, while the other set of signal lines creates the lower half of the image. An image signal for creating the frame of image is supplied to the two driver circuits alternately so that when one of the driver circuits is operating, the other is halted or put on standby.

Active matrix liquid crystal display

A scanning circuit for a display device having an array of pixels. One embodiment of the scanning circuit includes L scan control signal lines, first logic circuits to operate on signals from M of the L scan control signal lines, flip-flop circuits communicating with the first logic circuits, N timing control signal lines, and second logic circuits coupled to operate on signal from the N timing control signal lines and the flip-flop circuits.

The shift register of this invention for sequentially transferring a digital signal in synchronization with a clock signal includes: a plurality of circuit blocks connected in series, each including a prescribed number of sequential latch circuits, each latch circuit outputting a signal corresponding to an input signal based on the clock signal; and a plurality of clock signal control circuits provided for the respective circuit blocks for controlling the supply of the clock signal to the latch circuits in the corresponding circuit blocks, wherein the control of the supply of the clock signal by each clock signal control circuit to the latch circuits in the corresponding circuit block is conducted in response to output signals from prescribed latch circuits in the circuit blocks preceding and subsequent to the corresponding circuit block.

Shift register having a plurality of circuit blocks and image display

A matrix-type display device in which a number of pixels are arranged and a scanning line and a signal line to which a display signal is output are connected to each pixel. A signal line driver circuit in which a decoder circuit is controlled by a counter circuit, or a scanning line driver circuit in which a decoder circuit is controlled by a counter circuit is divided into a plurality of sections. A clock signal and/or a power supply voltage is selectively supplied to the respective sections.

Matrix-type display device

An active matrix liquid crystal electrooptical device consuming only a small amount of electric power without producing flicker. The electrooptical device comprises a plurality of pixels arranged in rows and columns. Each pixel has a switching element. Scanning lines for turning on and off the switching elements and signal lines to which display signals are produced are connected with the pixels. The device further includes plural signal line driver circuits. Each driver circuit produces a display signal to the corresponding signal line. Each display signal exhibits one polarity during one frame period. The polarity of the display signal produced by at least one of the driver circuits is different from the polarity of the display signal produced by the other driver circuit. The polarity is inverted every frame. The signal lines connected with any one of the driver circuits are connected with the pixels which are, in turn, connected with one of the scanning lines.

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Kanagawa, Japan

Hidehiko Chimura