Hitachi, Ltd.

Hidehiko Akita

Masahiro Kainaga

Kousuke Sakoda

Tomihiko Kojima

Tsutomu Miyairi

Tadashi Hirose

Hisashi Hashimoto

Fumiya Murata

Yoshitake Nakaosa

Masaharu Yabushita

Yutaro Hori

A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

Hierarchy structured memory system contained in a multiprocessor system

The present invention is directed to time-sharing computer system which includes a host computer system which operates in response to a host TSS command, a terminal computer system which is connected to the host computer system through a line and operates in response to a terminal TSS command, and a plurality of terminals which are connected to the terminal computer system. In this time-sharing system, the data processing in a terminal computer in response to a terminal TSS command input and the subsequent data processing in the host computer system in response to a host TSS command input can be carried out freely when the terminal is in a state of interaction with the host computer, without carrying out an end command of the host TSS a mode exchange operation. For this purpose, the system adopts the concept of a multiplexed TSS, which enables plural sessions to be simultaneously executed by the host computer system and the terminal computer system.

Time-sharing computer system operable in a host TSS mode and a terminal

A method of processing a plurality of different code systems for an information processing apparatus including an operating system, comprises a step of inputting a source program, and a compiling step of analyzing meaning of the source program to thereby create a series of instructions and data required for executing a processing equivalent to the meaning of the source program. The compiling step includes a sub-step of transforming character type constants to a first code system occupying region including a first number of bits and transforming character string constants to a second code system occupying a region including a number of bits which is equal to product of a sum of the number of characters of the character string constants plus one and multiplied with the first bit number so that character type variables designated in the source program correspond, respectively, to the region of the first bit number while a character type array corresponds to a region including a number of bits which is equal to a product resulting from multiplication of the first bit number with the number of elements of the array.

Method of processing a plurality of code systems

A computer system comprises a memory for storing communication history information between a terminal and an execution program, and an output message file for storing sets of communication history conditions and output messages corresponding to those conditions. When the terminal issues a message output request, only the output message that meets the communication history condition is selected from the output message file and outputted to the terminal.

Computer system

Growing community of inventors

Tokyo, Japan

Hidehiko Akita