Fujitsu Corporation

Hidehiko Akasaki

Haruo Kojima

Hiroyoshi Tomita

Yasurou Matsuzaki

Masao Nakano

Masataka Mizukoshi

Masahiro Sugimoto

Akira Takashima

Yasuhiro Fujii

Makoto Yanagisawa

Shinnosuke Kamata

Kiyoshi Miyasaka

Fumihiko Taniguchi

Tetsushi Wakabayashi

Takehisa Tsujimura

Toyonobu Yamada

Masami Matsuoka

Hideji Aoki

Koji Honna

Kazunari Kosakai

Toshihisa Higashiyama

Mamoru Yanagisawa

Kensaku Wada

The semiconductor device includes a semiconductor chip, an FPC tape for mounting the semiconductor chip thereto, a mold resin for protecting the semiconductor chip, and metal balls provided on the FPC tape for connecting the semiconductor chip to a circuit board. The mold resin has the glass transition temperature not lower than 200.degree. C., the coefficient of linear expansion in the range from 13 to 18 ppm/.degree. C., and Young's modulus in the range from 1500 to 3000 kg/mm.sup.2, whereby warpage of the semiconductor device is mitigated. The semiconductor device can also include a buffer layer. The semiconductor device can be manufactured by collectively molding a plurality of semiconductor chips mounted to the FPC tape and by cutting the molded article into individual semiconductor packages.

Resin molded semiconductor device and method of manufacturing

A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Semiconductor wafer testing method with probe pin contact

An integrated circuits package or a chip carrier having an integrated circuits chip sealed therein comprises layers of ceramic substrates, and terminal steps which are connected to inner pads in contact with the integrated circuits chip and which are provided on the bottom surface of at least one layer of the package, preferably the lowermost layer. The terminal steps are provided in a lattice arrangement, with so many rows of terminal steps as equals the number of terminal steps in one row, thus enabling connection of all of the terminals of the chip to outside wirings, such as wirings of a mother board.

Semiconductor device package

A semiconductor device module includes a package and a holder, the package includes, for example, a central processing unit, and the holder accommodates a removable leadless chip carrier. The holder comprising contact leads connected to electrode pads of the package. The leadless chip carrier also includes, for example, an erasable programmable read only memory, whereby the leadless chip carrier can be easily removed from the holder, resulting in easily writing into the erasable programmable read only memory or easy replacement of the leadless chip carrier.

Semiconductor device module

A package for a semiconductor device comprising three laminated ceramic sheets: a first sheet provided with a chip stage on the upper surface thereof, a second sheet provided with a first chip-inserting window for exposing the surface of the chip stage and provided with an internal conductor pattern formed at least on the upper surface thereof; and a third sheet provided with a second window for exposing the first chip-inserting window and for exposing a wire-bonding area located adjacent to the periphery of the first chip-inserting window, characterized in that marks for recognizing the location of the first chip-inserting window are essentially aligned, this alignment being effected in that the first chip-inserting window and marks for recognizing the location of the first chip-inserting window are simultaneously formed with the same mold, the marks for recognizing the location of the first chip-inserting window being formed in the wire-bonding area of the second green sheet.

Method for producing a package for a semiconductor device

A modular semiconductor device for use as a memory or used in logic circuit electronic equipment, includes a plurality of IC chips mounted on one or both sides of a printed circuit substrate. The IC chips are grouped into at least two groups which are selectively operated. The IC chips in one group are arranged alternately with the IC chips in the order group to provide a substantially uniform temperature distribution, over the substrate, of heat build-up in the substrate due to activation of the IC chips.

Modular semiconductor device

A semiconductor device includes a plurality of leadless packages and a base plate for mounting the leadless packages. The leadless packages include a semiconductor chip housed therein and a plurality of electrodes formed on the surface thereof. The base plate has conductor patterns formed on both of two main surfaces thereof, and the electrodes of each leadless package are soldered to the conductor patterns. The base plate also has a plurality of lead pins which project from one edge thereof in parallel with the main surface.

Semiconductor device including leadless packages and a base plate for

A hybrid integrated circuit device comprising in combination, a semiconductor integrated circuit element (1) and a film resistor pattern (7). The film resistor pattern is formed on the outer surface of a base (6) which is mounted on a multilayer ceramic package (2) which incorporates the element (1). In this assembled and operated hybrid device, function trimming of the film resistor pattern can be carried out by using a computer and testing is easier than is capable with prior art devices.

Hybrid integrated circuit device

Integrated circuit device

A package for enclosing semiconductor elements having side surfaces at which cross sections of conductive wires for receiving a voltage to effect electric plating are exposed. The side surfaces are provided with a static electricity-preventing device, such recesses formed in the side surfaces, insulating films formed on the side surfaces or removable frames positioned on the side surfaces, so that a high voltage due to static electricity from an exterior source is not applied to the conductive wires.

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Kawasaki, Japan

Hidehiko Akasaki