Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Other

Renesas Electronics Corporation

Hideharu Yahata

Yoshinobu Nakagome

Yuichi Okuda

Masaru Kokubo

Hiroki Miyashita

Masashi Horiguchi

Yoshikazu Saitoh

Sadayuki Morita

Kenichi Fukui

Yoji Nishio

Atsushi Hiraishi

Yasushi Kawase

Takahiro Sonoda

Tomohiro Nagano

Hirofumi Zushi

Haruko Kawachino

Masashige Harada

Hiroshi Toyoshima

Kunihiro Komiyaji

Hiroki Fujisawa

Tsugio Takahashi

Shinpei Iijima

Masayuki Nakamura

Takuya Fukuda

Yuzuru Ohji

Yasuhiro Sugawara

Shigeki Ueda

Ryouichi Furukawa

Misuzu Kanai

A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Semiconductor integrated circuit device

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

Semiconductor memory device

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory in formation from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.

The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.

Semiconductor memory

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.

Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate

A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually affected in the first memory operation and the second memory operation or the refresh operation.

In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register ( ) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit ( ) and a column decoder ( ).

Growing community of inventors

Inagii, Japan

Hideharu Yahata