Mitsubishi Denki Kabushiki Kaisha

Hideharu Toyomoto

Yuichi Nakao

Hiroyuki Kondo

Shohei Moriwaki

Naoichi Kitakami

Koji Tsuchihashi

Shunichi Yoshida

A processor containing a cache memory having its storage capacity enlarged while suppressing area increases is provided. The processor includes an SRAM (Static Random Access Memory) cache memory and a DRAM (Dynamic RAM) cache memory of a large storage capacity. The SRAM cache memory and the DRAM cache memory are coupled to the processor through a processor bus. The SRAM cache memory and the DRAM cache memory transfer data through an internal transfer bus provided separately from the processor bus and having a larger width.

Memory-contained processor

A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.

Refresh control circuit

A direct memory access controller has a data assembly function by means of a single temporary register. This single register used for a number of channels replaces temporary registers which have been necessary for the respective channels to carry out channel transition during data assembly. By controlling channel transition during data assembly, it is possible to carry out DMA transfers in which channel transition is made during data assembly, thereby preventing an increase in the chip size.

Growing community of inventors

Itami, Japan

Hideharu Toyomoto