Iwatsu Electric Company Ltd.

Hideharu Omori

Yoshihiro Kawata

Masayuki Kawashima

Toshimichi Shimatani

Yuji Kondo

Masaharu Kamigaki

Nobuyasu Shiga

Akira Hirato

Koichi Ichimura

Naoyuki Yamaguchi

Hironobu Oshikata

A synchronizing system in a digital communication line comprises a plurality of local switches for storing at least one digital line and monitoring a first piece of busy information when a clock source is already present, the local switches, if a first new clock source occurs while the first busy information is indicating no busy state, being capable of transmitting a master right request to turn the busy information to the busy state and to specify the first new clock source as a master clock and, on receiving a master right specification with respect to the master right request, being capable of outputting the first new clock source as the master clock; and a master switch connected to the plurality local switches in a star manner, by a link transmission line for transmitting control information including the master clock, master right request and master right specification, for monitoring a second piece of busy information indicating a busy state, the master switch, if a second new clock source occurs while the second busy information is indicating no busy state, being capable of transmitting the second new clock source as a master clock and, if the second new clock source competes with the first new clock source in the local switches that has output the master right request, being capable of arbitrating the competition between the first and second new clock sources and selecting one of the clock sources to turn the busy information to the busy state and, if the first clock source is selected, outputting the master right specification to the local switches that have transmitted the master right request.

Synchronizing system in digital communication line

A key telephone system for use in PCM telecommunications includes an office line communication units, an extension interface unit, a receiving unit, an extension communication unit, and an information transmitting and receiving unit. The system further includes a timing setting unit for setting the timings for transmitting and receiving information from and to each of the office line communication unit, the extension interface unit, the receiving unit, the extension communication unit, and the information transmitting and receiving unit in which downstream information, which is applied from the extension interface unit to a plurality of terminal units, contains a start bit, bits expressive of data information, and bits expressive of parity information in each of a plurality of frames, contains bits expressive of control information in at least one of the frames, and contains frame-synchronization information for achieving the synchronization of frames in at least one of the frames, and upstream information, which is applied from the terminal units to the receiving unit, contains the bits expressive of the data information, the bits expressive of the parity information, and the bits expressive of the control information, and one of the downstream and upstream information is sent in the former half of each of the frames, and the other thereof is sent in the latter half thereof.

Key telephone system

There is disclosed a data circuit-terminating equipment (DCE) which connects an asynchronous data terminal equipment (DTE) with a PCM trnsmission line having various speeds. Further the DCE can satisfy recomendations of the V25 bis of CCITT. The DCE includes a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make data from the DTE match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE. In the DCE satisfying the recommendations, the demapping circuit ANDs a clear-to-send signal and bits indicating the synchronized state to send the clear-to-send signal, and a short line shorting the clear-to-send signal and a carrier detect signal is employed.

Data circuit-terminating equipment

A time division multiplex telecommunications system is disclosed as adapted for a key telephone system providing for intercommunication between any two of a series of key telephone sets in cascade connection to a switching control circuit, possibly with facilities for association with the nationwide telephone network. The control circuit receives from the tandem connection of telephones an outgoing data signal of time division multiplex frame format having a succession of frames each comprising a frame sync signal and channels of outgoing data from the respective telephones. Rearranging the channels of data in the received outgoing data signal, the control circuits delivers back to the successive telephones an incoming data signal of similar frame format. Each telephone is equipped for rearrangement of the frame sync signal and data channels of the incoming and outgoing data signals, with the result that all the telephones can be of the same circuit configuration.

Time division multiplex telecommunications system and method for a key

Growing community of inventors

Tokyo, Japan

Hideharu Omori