Nec Corporation

Elpida Memory, Inc.

The University of Tokyo

Other

Ps4 Luxco S.a.r.l.

Hideharu Miyake

Hiroaki Ikeda

Kunihiko Nishi

Yasuhiro Naka

Masakazu Ishino

Hiroyuki Tenmei

Shiro Uchiyama

Nae Hisano

Shigeo Ohashi

Takuo Sugano

Yasuo Osone

Kiyonori Oyu

Koji Hamada

Kensuke Okonogi

Masaharu Watanabe

Yoichi Okabe

Naoki Fukaya

Yasushi Kozuki

A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

Semiconductor device having a liquid cooling module

A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusionwhich is provided in low melting point metalfor electrically connecting mutually joined wafersand, and which defines an interval between mutually joined wafersandwithout being deformed at the time when low melting point metalis melted. A joining structure of wafersandis manufactured by using wafersand, at least one of which has protrusion. In the manufactured joining structure of wafersand, wafersandare electrically connected to each other by low melting point metal, and protrusion, which defines the interval between wafersandwithout being deformed at the time when low melting point metalis melted, is provided in low melting point metal

Wafer of circuit board and joining structure of wafer or circuit board

A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.

Semiconductor chip with a porous single crystal layer and manufacturing method of the same

The invention provides a stacked capacitor cell structure for a semiconductor memory device. The cell includes a transistor formed in an active region in a surface of a semiconductor substrate; a first inter-layer insulator both overlying the transistor and having a contact hole over the transistor; a second inter-layer insulator both overlying the first inter-layer insulator and having a through hole with a larger diameter than the diameter of the contact hole; a stacked capacitor both formed within the through hole formed in the second inter-layer insulator and comprising a storage electrode electrically connected to the transistor through the contact hole, a capacitive insulation film and an opposite electrode; and a third inter-insulator overlying both the stacked capacitor and the second inter-layer insulator.

Semiconductor memory device having improved stacked capacitor cells

A semiconductor memory device having stacked-capacitor type memory cells, each of which contains an MOS transistor and a storage capacitor. The capacitor has a first opposed electrode having a recess at its upper face, which is formed through an inter-layer insulation film on the substrate, a first insulation film which covers a surface of the first opposed electrode, a charge storage electrode formed in the recess of the first opposed electrode and contacted with the source region of the transistor through a contact hole of the inter-layer insulation film, a second insulation film which covers a surface of the charge storage electrode, and a second opposed electrode formed on the second insulation film. The charge storage electrodes do not broken in the fabrication sequence of the device. Even if the charge storage electrodes are sheered off in positioning to the corresponding contact holes, the inter-layer insulation film is disadvantageously etched.

Method for fabricating a semiconductor memory device having stacked

Semiconductor memory device and its fabrication method

An intermittent etching process for forming efficiently by reactive ion etching (RIE), a minute recess, such as a groove having an opening width as small as about 0.1 .mu.m, with a large aspect ratio in layers of metals, semiconductors, etc. The process comprises alternating RIE steps of brief duration e.g. 30 seconds with vacuumizing for evacuating gaseous reaction products produced in the RIE step from the etched recess. The process is particularly suitable for formation of a bridging portion of Nb, etc. constituting Josephson devices, by making use of three layered resist technique.

Intermittent etching process

A superconducting logic circuit has a first and a second one-junction SQUID's (superconducting quantum interference device) connected by a superconducting inductor, the junction of the second SQUID having a larger critical current than that of the first SQUID, the inductance of the second SQUID being smaller than that of the inductor, and a signal applied to the first SQUID is unidirectionally transmitted to the second SQUID by applying bias currents to the junctions of the two SQUID's.

Unidirectional single-flux-quantum logic circuit

Growing community of inventors

Tokyo, Japan

Hideharu Miyake