Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Winbond Electronics Corporation

Toshiba Shibaura Denki Kabushiki Kaisha

Hideharu Koike

An input circuit including a diode, a resistor, a first transistor, a buffer, a bulk voltage generating unit and an enhancing unit is provided. The input circuit of the present invention uses the bulk voltage generating unit and the enhancing unit for making the internal input voltage to be the same as the external input voltage when the external input voltage is less than or equal to the first supply voltage (for example, the IO supply voltage). Moreover, even if the first supply voltage is extremely low, the input circuit of the present can still operate correctly. Accordingly, the input circuit of the present invention can be operated at extremely low IO supply voltage.

High voltage tolerant input circuit capable of operating at extremely low IO supply voltage

The LVDS receiver circuit comprises a differential-input transistor pair, a control transistor pair, a current-mirror-load circuit, a first feedback inverter and a second feedback inverter. The first feedback inverter, the second feedback inverter and the control transistor pair constitute a feedback loop. The voltage change of the input voltage of the first feedback inverter is suppressed, and the input voltage is controlled around the threshold voltage of the first feedback inverter.

LVDS receiver circuit

A comparator according to one embodiment includes first and second input terminals, first and second output terminals, first and second input inverters, first and second load inverters, and a bias control circuit to provide first and second bias voltages for application to inputs of the first and second load inverters, respectively.

Comparator

The asynchronous sense amplifier for a ROM includes a current-mirror circuit, a first negative feedback inverter, a second negative feedback inverter, a first transistor group, a second transistor group and a feedback transistor. The feedback transistor connects the junction of the first transistor group and the first set of the current-mirror circuit and/or the junction of the second transistor group and the second set of the current-mirror circuit to ground, where the feedback transistor is controlled by the output of the first negative feedback inverter and/or the second negative feedback inverter, and the feedback transistor is smaller than one transistor of the second transistor group.

Asynchronous sense amplifier for read only memory

A differential difference amplifier includes a first pair of differential input terminals and a second pair of differential input terminals. The differential difference amplifier has a pair of differential output terminals to output a voltage in relation to a difference between differential voltages at the first pair of differential input terminals and differential voltages at the second pair of differential input terminals.

Differential difference amplifier

CMOS buffer circuits with reduced short circuit current. In the CMOS buffer circuit, an output stage drives an output terminal and comprises a first output transistor of a first conductive type and a second output transistor of a second conductive type. An output driving unit produces a first signal to turn off the first output transistor according to a delay signal. A bidirectional delay unit is controlled by the input signal to turn on the second output transistor after the first output transistor be turned off. In the bidirectional delay unit, a bidirectional logic unit generates two logic signals according to an inversion signal of the input signal, first and second bidirectional buffers are coupled to the output driving unit, generating a second signal to turn on the second output transistor according to the input signal and the two logic signals.

CMOS buffer circuits and integrated circuits using the same

A noise filter for an integrated circuit is proposed. The noise filter comprises a CMOS inverter and two capacitors. The input of the CMOS inverter is coupled with an input pad of the integrated circuit and the output of the CMOS inverter is coupled with an input buffer. The first capacitor is inserted between the output of the CMOS inverter and a first voltage source and the second capacitor is inserted between the output of the CMOS inverter and a second voltage source. A transfer gate may be in stead of the CMOS inverter.

Noise filter for an integrated circuit

The present invention discloses a spike free circuit, which comprises a first flip-flop stage, a time shift means, a group of logic gates and a second flip-flop stage. The first flip-flop stage is triggered by a first edge of a clock signal. The time shift means is electrically connected to the first flip-flop stage and triggered by a second edge opposite to the first edge of the clock signal. The time shift means shifts input signals, which change logic level within the first to the second edges of the clock signal one half cycle for preventing spike occurring. The group of logic gates is connected to the time shift means. The second flip-flop stage is electrically connected to the group of logic gates and triggered by the first edge of the clock signal.

Spike free circuit for reducing EMI effect

Two pairs of differential input voltages are converted into two pairs of differential voltages through voltage converters whose output voltages are determined only by the input voltage amplitudes. Of the two pairs of differential input voltages, a voltage across the positive terminals and a voltage across the negative terminals of the voltage converters are converted into two pairs of differential currents through voltage-to-current converters. An output voltage proportional to the difference between the two pairs of differential currents is obtained with improved linearity through a current-to-voltage converter.

Voltage conversion circuit and differential difference amplifier

An amplifier circuit influenced less by an offset voltage and capable of permitting an as broad as possible dynamic range is provided. This amplifier circuit includes first and second MOS transistors M1, M2; a first operational amplifier OP1 having an inverting input terminal connected to the drain of the first MOS transistor and a non-inverting input terminal connected to the drain of the second MOS transistor; a second operational amplifier OP2 having two input terminals such that one input terminal is connected to the drain of the second MOS transistor and the other input terminal is connected to a second power supply VD; a first resistance circuit provided between the drain of the first MOS transistor and the output terminal of the first operational amplifier; a second resistance circuit having the same resistance value as that of the first resistance circuit provided between the drain of the second MOS transistor and a third power supply VC; a first load circuit for delivering load current to the drain of the first MOS transistor; and a second load circuit for delivering load current of the same value as the load current to the drain of the second MOS transistor, thus to control load currents flowing in the first and second load circuits by the output of the second operational amplifier so that the drain voltage of the second MOS transistor becomes equal to the second power supply voltage.

Amplifier circuit with small offset voltage influence

A voltage divider circuit comprises first and second transistor pairs 1 and 2 connected in series between a first standard voltage terminal VD and a second standard voltage terminal VS, and feedback control circuit 3. Each of transistor pairs comprises two NMOS transistors with the same electric characteristics, respectively. A divided ratio is set by a voltage applied to the gate terminals of these NMOS transistors M1-M4. Feedback-control circuit 3 comprises a load transistor pair 4 and an operational amplifier OP1. The circuit 3 performs feedback-control so that a voltage of connection lines L1 and L2 which connects first and second pairs of transistors becomes equal. Therefore, a high accurate divided voltage is outputted from between pairs 1 and 2 of transistors.

Voltage divider circuit, differential amplifier circuit and

A voltage subtracter circuit of the present invention includes a constant current source 1, a first MOS transistor pair 2, one end of which is connected to a source voltage terminal, and a second MOS transistor pair 3, one end of which is connected to the constant current source 1. A first differential input voltage is applied between the gate terminals of the first transistor pair 2, and a second differential input voltage is applied between the gate terminals of the second transistor pair 3. Output terminals V1 and V2 are connected to the connecting point between the first and second transistor pairs 2 and 3. From these nodes V1 and V2, a differential voltage between the first differential input voltage and a differential voltage proportional to the second differential input voltage is outputted. According to the present invention, this voltage subtracter circuit does not have any resistors, so that the circuit can be easily integrated and operated with high accuracy without being influenced by Vth and so forth.

Voltage subtracter circuit, voltage amplifier circuit, voltage divider

The latch circuit comprises a data hold circuit comprising a closed loop circuit formed by an even number of stages of logic gates connected in series. The data hold circuit accepts data when a clock signal is received and holds this data until a next clock signal is received. A filter is provided for eliminating pulses generated in the closed loop circuit. The filter is formed of logic gates.

Latch circuit including filter for metastable prevention

A low pass filter which has a plurality of NAND gates connected in series. Input signals are input directly to one input terminal of each of the respective NAND gates, respectively. Input signals are input through a plurality of inverters to the NAND gate of the initial stage. The NAND gate of the final stage is connected through even number of inverters to a circuit output node N2. An odd number of inverters are provided between the preceding and following NAND gates.

Low pass filter formed in an integrated circuit

A full-adder circuit comprising a first node for providing an inverted summed output, a second node for providing an inverted carry output, a plurality of P channel MOS FETs connected between a Vcc terminal and the first and second nodes to form a first circuit pattern, the P channel MOS FETs being applied at the gates with an addend input signal of N-bits (N is a natural number of 1 or more) and an augend input signal of N-bits, a carry input signal of one-bit, and the one-bit inverted signals of the input signals, a plurality of N channel type MOS FETs connected between a Vss terminal and the first and second nodes to form a second circuit pattern which is substantially the same as that of said first circuit pattern, said N channel type MOS FETs being applied at the gates with the same addend, augend and carry inputs as those applied to the P channel type MOS FETs in a similar manner, a first inverter connected between the first node and a summed output terminal and for inverting a signal at the first node, and a second inverter connected between the second node and a carry output terminal and for inverting a signal at the second node.

Growing community of inventors

Yokohama, Japan

Hideharu Koike