Matsushita Electric Industrial Co., Ltd.

Matushita Electric Industrial Co., Ltd.

Hidefumi Otsuka

Tomonori Fujimoto

Yuji Yamasaki

Shoji Sakamoto

A semiconductor integrated circuit includes a plurality of semiconductor memory devices implemented as DRAMs and an output selector on the same chip. External terminals of the chip include: terminals for inputting an inverted row address strobe signal /RAS to the respective semiconductor memory devices individually; and common terminals for inputting PRAUT, SLF, /CAS, ADR, /WE, /OE, CLK and TMODE signals to all the memory devices. The output signals TDQ, SRAS, MOUT and BITST of the semiconductor memory devices are controlled by the output selector, passed through a common test bus and then output from a common external terminal.

Semiconductor device

A dynamic random access memory (DRAM) whose charge-holding characteristic regarding a leak of an electric charge through the bit line is tested in a short time is provided. The DRAM comprises a memory cell array including memory cells arranged at intersections of word lines and bit lines, plural sense amplifiers disposed at a pair of the bit lines, plural bit line pre-charge circuits for pre-charging and equalizing a potential in the pair of the bit lines, and a switching circuit for selecting an ordinary operation mode or a test mode. It further comprises a word line deactivator for deactivating all of word lines in the test mode, a sense amplifier deactivator for deactivating all of sense amplifiers in the test mode, and a bit line potential fixing circuit for fixing the bit lines to the same logic level of a high or a low level in the test mode.

Semiconductor storage device and method of testing the same

For enabling the self-test of a memory with a small number of input and output pins, and the burn-in tests of a memory and a logic to be carried out simultaneously in a memory/logic circuit mixed system LSI, a test data, an address and a memory control signal required for the test of the memory are generated using the divided-frequency output signal of an address generator, i.e., frequency-divider of an external clock, and a mixer circuit for periodically inverting a pass/fail signal as the test result is provided. This enables the test of the memory with a total of 2 pins of input and output in all. Thus, it becomes possible to test the memory and the logic circuit simultaneously at the time of burn-in test thereof.

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Osaka, Japan

Hidefumi Otsuka