Hitachi Ulsi Systems Co., Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hidefumi Oodate

Kunihiro Katayama

Motoki Kanamori

Atsushi Shiraishi

Shigeo Kurakata

Atsushi Shikata

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controllerto the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Memory card and its initial setting method

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data. FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.

Non-volatile memory card and transfer interruption means

In the initial setting of a memory card, the flash check data FD stored in a flash memoryis read out, this data FD is compared with the operation check data FDstored previously in the ROM, the write check data FDstored in the ROMis written, if a fault is not detected, to the flash memory, and this data is read again and is compared with the write check data FDof the ROM. When any fault is not detected in comparison of these data, the CPU determines that the flash memoryis normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a registerto set a controllerto the sleep mode. When the command CMD is received during this period, data comparison is executed again.

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Kodaira, Japan

Hidefumi Oodate