Sanyo Electric Co., Ltd.

Other

Hidefumi Okada

Akio Kobayashi

Haruhiko Murata

Toru Asaeda

Hirokazu Ide

Yukio Mori

Akihiro Maenaka

Atsushi Kobayashi

Mitsuaki Kurokawa

Yasuhiko Naito

Tomio Ishigamii

An image processing apparatus () includes a bus (B) and a bus (B). A series of processes for creating YUV image data for HDTV is executed by means of a bus (B) and an SDRAM (). Furthermore, a series of processes for creating YUV image data for LCD monitor () is executed by means of a bus (B) and an SDRAM (). Here, the resolution of the YUV image data for HDTV is higher than that of the YUV image data for LCD monitor. That is, the bus (B) and the SDRAM () are utilized for high-resolution moving image data processing, and the bus (B) and the SDRAMare utilized for low-resolution moving image data processing.

Image processing apparatus

A digital camera includes a CCD imager which outputs 640 pixels&#xd7;480 lines of camera signal in a raster scan scheme. The camera signal outputted from the CCD imager is subjected to a predetermined signal processing whereby created are 640 pixels&#xd7;480 lines of original image data and 80 pixels&#xd7;60 lines of thumbnail image data. Both the created original image data and thumbnail image data are written to a SDRAM. The writing of the thumbnail image data is performed during a horizontal blanking period of the original image data. As a result, image data writing operation completes within a 1-frame period of time.

Digital camera

An edge emphasizing circuit includes a first high-frequency detection circuit and a second high-frequency detection circuit. A spatial frequency of a raw image signal corresponding to a photographed object is detected by the first high-frequency detection circuit or the second high-frequency detection circuit, and a gain corresponding to a detection result is made effective. The gain to be made effective is decreased as the spatial frequency of the raw image signal is low. The gain is applied to an edge emphasizing signal generated by the edge emphasizing circuit, and the raw image signal is added to the edge emphasizing signal to which the gain is applied. Thus, a raw image signal with an emphasized edge is obtained.

Edge emphasizing circuit

A digital camera includes a CCD imager having an interline transfer scheme. A first charge produced due to first exposure is read from light receiving elements positioned vertically intermittently. A second charge produced due to second exposure is also read from the same light receiving elements to vertical transfer regions. Here, the first charge is vertically moved simultaneously with or prior to reading out the second charge. The moving distance, at this time, is equal to or greater than a distance that the light receiving elements continue in the vertical direction. As a result of this, the second charge will not be mixed with the first charge. The first and second charges are subjected to a compositing process to display a composite image on an LCD.

Digital camera which produces a single image based on two exposures

A digital camera includes a CCD imager mounted at a front with a primary color filter. An optimal shutter speed is calculated based on a camera signal outputted from the CCD imager upon a pre-exposure. Where a calculated optimal shutter speed is low, a timing generator drives the CCD imager by a pixel-mixing scheme. Charges are first read out of part of the light receiving elements and transferred in a vertical direction. When the charges are transferred by a predetermined distance, the remaining part of the light receiving elements are read out. As a result of this, the charges of a same color of color components are mixed together. That is, a filtering process is effected within the CCD imager to remove aliasing components.

Imaging apparatus and digital camera

Digital camera includes a CCD imager having VGA resolution. The camera signal of subject image taken by the CCD imager is subjected to a predetermined process by a signal processing circuit, whereby image data is created having 640 pixel&times;980 lines. Meanwhile, a CPU enables cut-out circuit when a 1-tims mode is set by a zoom button, and a cut-out circuit when a 2-times mode is set by the zoom button. The thin-out circuit performs thinning out pixel data, every other pixels and lines, on the image data having 640 pixels&times;480 lines, outputting image data having 320 pixels&times;240 lines. The cut-out circuit cuts 320 pixels&times;240 lines of image data from a center of the image data of 640 pixels&times;480 lines.

A digital camera includes a mode set switch. If a camera mode is set by mode set switch, the image data corresponding to a subject image taken by a CCD imager is processed by DMA, and outputted through a first bus onto a monitor. If a shutter button is operated, the first bus is connected to a second bus by a bus bridge and the image data is transferred from a first bus side to a second bus side. On the second bus side, the CPU processes the image data according to a program and records it on a memory card.

Digital camera using separate buses for transferring DMA processed data and CPU processed data

A digital video camera includes an addition circuit in which an offset set by a CPU is added to an output from an A/D converter. A clamp level calculation circuit calculates a clamp level on the basis of an average level of eight pixels included in each line within a back end OB (optical black) level detection area in a normal mode, or calculates a clamp level on the basis of an average level of two pixels included in each line within a front end OB level detection area in a quadruplication mode. A first subtraction circuit subtracts the clamp level from an output of the addition circuit so as to clamp the output of the addition circuit. An output of the first subtraction circuit is clipped at a zero-level by a zero-clipping circuit, and an output of the zero-clipping circuit is applied to a second subtraction circuit through a low-pass filter, whereby the same offset can be subtracted from the output of the zero-clipping circuit.

Digital video camera with high-speed mode

A CCD portion is driven by a driving circuit for separately reading out all pixels. Data for 4 lines are input in parallel to a two-dimensional register array by scanning line delay devices, and an interpolation processing is performed for each of color signals G, Mg, Cy and Ye based on data corresponding to pixels in a 4 row by 4 column matrix. Color difference signal generation circuit performs a color separation processing based on thus interpolated color signals.

Color camera having a single imaging element and capable of restricting

A 1-chip color video camera which provides a frequency characteristic that exhibits relatively little attenuation up to a high frequency range for a (green) signal and has a highest degree of contribution to brightness, and hence provides high resolution. The 1-chip color video camera has a color separation circuit for processing signals obtained from a solid-state image sensor wherein primary color filters of R(red), G and B(blue) are arranged mosaic-wise for respective pixels. Color signal components at a central portion of a pixel block consisting of four pixels of two rows by two columns on the solid-state image sensor are generated by interpolating color signal components of a plurality of neighboring pixels.

1-chip color video camera for generating inter-pixel color signal

The digital dividing apparatus includes a comparator for comprising a first input signal A with a second input signal B; a selector responsive to an output from the comparator for selecting a larger one out of the first and the second input signals; a priority encoder for outputting a priority signal in which only a bit corresponding to the most significant bit out of bits having a value of '1' of the selected input signal is set to a value '1'; a bit difference encoder responsive to the priority signal for producing a bit difference between the most significant bit of the selected input signal and the most significant bit out of bits having a value of '1' of the selected input signal; a first shifter for shifting the first input signal A to an upper side by the bit difference; a second shifter for shifting the second input signal B to an upper side by the bit difference; a first round-down circuit for rounding down lower bits of the signal shifted by the first shifter to produce a first m-bit round-down signal .alpha.; a second round-down circuit for rounding down lower bits of the signal shifted by the second shifter to produce a second n-bit round-down signal .beta.; a LUT memory for pro-storing a look-up table; and an LUT control circuit for controlling the LUT memory.

Digital dividing apparatus using a look-up table

A gamma correction circuit including a first look-up table in which minimum values of differences between output levels of a gamma correction curve and output levels of a straight line in respective sections formed by dividing a range from a minimum input level to a maximum input level into sixteen are stored. Furthermore, data of differences between the output levels of the gamma correction curve and levels obtained by adding the minimum values to the output levels of the straight line in the respective sections are stored in respective second look-up tables of sixteen. Then, one of the minimum values is read-out from the first look-up table according to upper four bits of input video data, and one of the second look-up tables is selectively enabled by the upper four bits, and data stored in the selected second look-up table is read-out in accordance with lower six bits of the input video data. Outputs from the first and second look-up tables are added to each other so as to output gamma correction data which is then added to the input video data, whereby a gamma characteristic of the input video data is corrected.

Gamma correction circuit for correcting video data obtained by

A signal processing circuit is utilized in a video camera which includes a CCD having pixels arranged in a dot-matrix fashion and color filters of R, G and B arranged in a mosaic fashion, and an output signal from the CCD is converted into a digital signal. A horizontal aperture signal (Hap) and a vertical aperture signal (Vap), which are produced on the basis of the digital signal, are multiplied by coefficients (K1, K2) which are obtained on the basis of a horizontal correlation value (Sh) and a vertical correlation value (Sv), and then, added to each other in an adding circuit, whereby an aperture signal is obtained by the adding circuit. The aperture signal is added to a luminance signal to perform an image enhancement.

Signal processing circuit for video camera which prevents a false

A color video camera includes a CCD, and digital signals of 4 lines produced on the basis of an outputs from the CCD are applied to a selection circuit which selectively outputs digital signals of 3 lines. A horizontal interpolation circuit and a vertical interpolation circuit perform interpolation calculation on the basis of the digital signals, and outputs a plurality of horizontal color signals and a plurality of vertical color signals, respectively. A horizontal correlation detection circuit and a vertical correlation detection circuit evaluate a horizontal correlation value and a vertical correlation value of a specific pixel with respect to pixels around the specific pixel. Horizontal and vertical weighing coefficients are calculated by a coefficient calculation circuit in accordance with the correlation values, and the coefficients are applied to a weighted addition circuit which adds the horizontal color signals and the vertical color signals to each other for each color in accordance with the coefficients, and outputs the color signals of the specific pixel.

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Daito, Japan

Hidefumi Okada