Kabushiki Kaisha Toshiba

Hidefumi Nawata

Kikuko Sugimae

Akihiro Kajita

Kiyomi Naruke

Takamichi Tsuchiya

A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.

Nonvolatile semiconductor memory device

A bit line is electrically connected to one end of a current path of a memory cell. A word line is commonly connected to the memory cells arranged in a direction intersecting the bit line. A control circuit executes a write operation for applying a write voltage to the word line so shift a threshold voltage of the memory cell to be data written that the threshold voltage of the memory cell to be data written reaches a certain threshold voltage. During the write operation, the control circuit, while applying a gradually rising write voltage to the word line, gradually changes a voltage applied to the bit line based on a relationship between the threshold voltage of the memory cell to be written and a number of times of the write voltage applications.

Nonvolatile semiconductor memory device and method of data write therein

A non-volatile semiconductor storage device according to an embodiment includes a memory cell array and a control circuit configured to execute a read operation. The control circuit refers to data of a reference memory cell which is adjacent to a selected memory cell and in which data is written after a data write operation on the selected memory cell. The control circuit applies a first read pass voltage to a non-selected word line adjacent to the selected word line, when the data of the reference memory cell is data causing the shift of the threshold voltage of the selected memory cell. The control circuit applies a second read pass voltage lower than the first read pass voltage to the non-selected word line, when the data of the reference memory cell is data not causing the shift of the threshold voltage of the selected memory cell.

Non-volatile semiconductor storage device having a control circuit configured to execute a read operation

A nonvolatile semiconductor memory device according to an embodiment includes a control unit configured to perform a control of repeating a program operation, and a step-up operation, the program operation being an operation of applying a program pulse voltage to a selected memory cell and applying an intermediate voltage less than the program pulse voltage to first and second non-selected memory cells adjacent to the selected memory cell, and the step-up operation being an operation of increasing the program pulse voltage by a first step-up value. For a first period, the control unit maintains the intermediate voltage to be a constant value. For a second period, the control unit controls the step-up operation such that the intermediate voltage is increased by a second step-up value, and determines the first step-up value on the basis of the second step-up value.

A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a write voltage to the word line. The control circuit is configured to execute a correction write operation accompanied by the write operation and executed on a selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.

Non-volatile semiconductor storage device

A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state.

Nonvolatile semiconductor memory device and writing method thereof

A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.

Growing community of inventors

Kawasaki, Japan

Hidefumi Nawata