Mita Industrial Co., Ltd.

Kyocera Mita Corporation

Hidechika Kumamoto

Masaya Fujimoto

Haruo Yamamoto

Shinji Hayashi

Tsukasa Matsushita

Tadashi Miyazaki

Masayuki Mizuno

Katsuyuki Teranishi

Akira Shimatani

Setsuo Hori

Satoshi Kuroyanagi

This image forming devicecomprises an image processing unit, an HDDand an image forming unit. The image processing unitis capable of instructing the output of the image data sent from the PC. The HDDis connected to the image processing unitand is capable of storing the image data to be delivered. The image forming unit is capable of receiving the instruction from the image processing unitand delivering onto paper or the like the image data stored in the HDD. Then, when the ID information contained in the image data is detected by the image processing unit, writing of image data to the HDDis prohibited.

Image forming device and image forming system

This image forming devicecomprises a control unit, a connector interface, an external memory, and an image forming unit. The control unit instructs the output of a predetermined image data. The connector interfaceis connected to the control unit. The external memorycan be removably connected to the connector interfacewhile it stores the output image data. The image forming unit is capable of receiving the instruction from the control unit and delivering onto paper the image data stored in the external memory

Image forming device

An apparatus for and a method of reliably detecting a very small dotted image area. A detecting area including a predetermined number of pixels including a target pixel is set. It is judged whether or not the detecting area belongs to a dotted image area on the basis of the number of edge pixels in the detecting area. Consequently, it is possible to detect edges peculiar to the dotted image area on the basis of a leading edge portion or a trailing edge portion of the density, to detect the very small dotted image area on the basis of the number of edge pixels.

Dotted image area detecting apparatus and dotted image area detecting

An image processing circuit which adds, by means of a yellow color image data, forgery tracing information to yellow, magenta and cyan color image data obtained by reading out of an original. A tracing information adder replaces the read-out yellow color image data with a yellow color image of a higher density in a low-density area where the density of the read-out yellow color image data is equal to or below a set threshold value. In a high-density area where the density of the read-out yellow color image data exceeds the set threshold value, the tracing information is added by adding a predetermined value to the read-out yellow color image data.

Image processing circuit

An apparatus for and a method of detecting a dotted image area in an image. It is judged on the basis of image data corresponding to pixels in a first judging area which includes a predetermined number of pixels including a target pixel whether or not the target pixel is a peculiar point pixel (a peak pixel or a dip pixel). Further, it is judged on the basis of image data corresponding to pixels in a second judging area which is larger than the first judging area whether or not the target pixel is a peculiar point pixel. The dotted image area in the image is detected on the basis of the results of judgment related to the first judging area and the second judging area.

Apparatus for and method of detecting dotted image area using two types

Disclosed is an apparatus for detecting pixels in a dotted image area (dotted area pixels). Image data corresponding to each of the pixels is coded into one of a predetermined number of discrete values. The distance between change points at which the value of the pixel after the coding is changed from a first value to a second value is detected. Further, it is examined whether or not periodicity is recognized in the distance between the change points in the vicinity of a target pixel. If periodicity is recognized in the distance between the change points, it is judged that the target pixel may constitute a dotted image area.

Method of and apparatus for detecting pixels constituting dotted image

An apparatus for and a method of judging a dotted image area using a small-capacity memory. Image data corresponding to one line out of image data representing an original image are stored in a line memory. On the line corresponding to the image data stored in the line memory, a target pixel is successively set along the main scanning direction. Image data corresponding to the target pixel is compared with image data corresponding to pixels around the target pixel. It is judged whether or not the target pixel is a peculiar point pixel on the basis of the result of the comparison. Further, the distance between peculiar point pixels is operated. The operated distance between the peculiar point pixels is referred to a predetermined judgment basis, to judge whether or not a judging area including the finite number of pixels is a dotted image area.

Apparatus for and method of judging dotted image area

A color image is by an optical scanner for conversion into three primary color data corresponding to the respective densities of the three primary colors. An edge detector detects a pixel of an edge based on the three primary color data. A pixel color judging device judges a color of a target pixel based on the three primary color data of the target pixel and its adjacent pixels. Based on edge detection results of the edge detector and pixel color judgment results of the pixel color judging device, detected is a pixel of a black edge. Judgement conditions for the pixel color judgement are established based upon characteristics that depend upon the order of arrangement of color filters in a scanner.

Image processing apparatus

An image processor performs emphasis processings suitable for materials to be copied to produce clear copy outputs. The image processor has a digitizing circuit which outputs a digital signal produced by digitizing an image. The processor further has a first detecting circuit which detects an area of the digital signal including a periodic component, a second detecting circuit which detects a character area of the digital signal, and a smoothing circuit which smoothes the digital signal to output a smoothed signal. Either the digital signal or the smoothed signal is selected and outputted by a changeover circuit according to an output of the first detecting circuit. The output of the changeover circuit is differentiated into a plurality of differentiated signals by a differentiating circuit by use of a plurality of different coefficients. One of the differentiated signals is selected and outputted according to the outputs of the first and second detecting circuits.

Image processor for smoothing and differentiating periodic areas and

A synchronization signal generating circuit generates a synchronization signal used to output read data sequentially in a specified period. This circuit is provided with a clock generator means for generating a reference clock, a first counter unit for counting the reference clock; a synchronization signal generator for generating the synchronization signal in a first period in accordance with a count value of the first counter unit; a second counter unit for counting the generation of the synchronization signal; a resetter for resetting the second counter unit when a count value of the second counter unit reaches a specified value; and a period changer for controlling the synchronization signal generator so as to generate the synchronization signal in a second period only when the count value of the second counter unit reaches the specified value. Accordingly, a shift amount of the period of the synchronization signal relative to the specified period in which data are output sequentially does not exceeds a predetermined level.

Synchronization signal generating circuit

A skew processing circuit 33 includes two line buffers, a skew processing type line buffer 331 and an original type line buffer 332, and a write/read control circuit 333 for controlling the two line buffers. The write/read control circuit 333 is a control circuit for writing a given image data in the line buffers 331, 332 in single lines and selectively reading the data written in the two line buffers 331, 332. When an image data is written in the original type line buffer 332, addressed are sequentially written from the head address 0. On the other hand, when the image data is written in the skew processing type line buffer 331, a write start address RH0 is determined in correspondence with a skew angle, and the write start address RH0 is shifted in each line to discard the head portion of the image data by specified dots (specified addresses). Thus, by controlling the writing of data in the two line buffers 331, 332 and reading data from them, an image in an arbitrary area can be processed into the skew with an arbitrary angle.

Skew processing circuit and method of calculating a preset value for the

A laser beam controller comprises a basic pulse signal generating circuit, a delay circuit, a delay control circuit, a pulse generating circuit and a laser beam generator. The basic pulse signal generating circuit generates periodically occurring basic pulse signal. The delay circuit delays the basic pulse signal. The delay control circuit controls the delay time of the basic pulse in the delay circuit according to image data. The pulse generating circuit generates an output pulse having a width corresponding to the delay time of the basic pulse signal. The laser beam generator generates a laser beam for a duration corresponding to the width of the output pulse by said pulse generating circuit. According to the controller, any desired gradation of a pixel of the image is desirably produced.

Laser beam controller

A shadow-added image formation device includes a photoelectric converting mechanism for converting every pixel into an electric signal, A/D-converting mechanism for A/D-converting an output of the photoelectric converting mechanism, a signal converting mechanism for converting an output of the A/D-converting mechanism into a binary serial signal representing white and black pixels, and a detecting mechanism for detecting an area to which shadow can be added from the output of the signal converting mechanism. A shadow signal formation mechanism for outputting a signal, a setting mechanism for setting a shadow area, an adding mechanism for comparing the widths of the areas detected by the detecting mechanism and set by the setting mechanism and adding the shadow signal to the binary serial signal corresponding to the smaller one of the areas determined by the comparison, and a reproducing mechanism for reproducing an image to which the shadow signal has been added, are also provided.

Shadow-added image formation device

An integrated circuit (IC) card for use in an image processing machine, such as a digital copying machine. The IC card includes a first storage area for storing data for controlling said image processor and a second storage area for storing image data to be processed by said image processor.

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Osaka, Japan

Hidechika Kumamoto