Sharp Kabushiki Kaisha Corporation

Sharp Laboratories of America, Inc

Sharp Microelectronics Technology, Inc.

Xenogenic Development Limited Liability Company

Hidechika Kawazoe

Sheng Teng Hsu

Yukio Tamai

Katsumasa Fujii

Eiji Aoki

Atsushi Shimaoka

Nobuyoshi Awaya

Hidetoshi Masuda

Jong Jan Lee

Toshimasa Suzuki

Naoto Hagiwara

Shinji Kobayashi

Hidenori Morimoto

Yuji Matsushita

Yuji Nishi

A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell () array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WLto WLn), the memory cells in a column are connected at the other end to common bit lines (BLto BLm), and a common unselected voltage V/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.

Nonvolatile semiconductor storage device and method for operating same

A nonvolatile semiconductor storage device is provided with a memory cell selecting circuit which selects a selected memory cell from a memory cell array; and a write voltage applying circuit, which applies a row write voltage and a column write voltage to a selected word line and a selected bit line, respectively, and applies a row write blocking voltage and a column write blocking voltage to an unselected word line and an unselected bit line, respectively, and applies a write voltage sufficient for writing only on both ends of the selected memory cell. The write voltage applying circuit applies a write compensating voltage, which has a polarity opposite to that of the voltage applied on the both ends of the unselected memory cells other than the selected memory cell, on both ends of the unselected memory cells, while the write voltage is applied to the selected memory cell.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

Nonvolatile semiconductor memory device and read method

A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, PrCaMnO, that has been formed at a film forming temperature from 350&#xb0; C. to 500&#xb0; C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.

In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.

Nonvolatile semiconductor memory device comprising a variable resistive element containing a perovskite-type crystal structure

An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.

Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same

A protection circuit for protecting a semiconductor device from being damaged due to an excessively high applied voltage, includes a P-type MOS transistor provided between an external input-output terminal and a power supply line, an N-type MOS transistor provided between the P-type MOS transistor and a ground line, a first thyristor provided between the external input-output terminal and the ground line, the anode portion being connected to the external input-output terminal side, and the cathode portion being connected to the ground line, a second thyristor provided between the power supply line and the ground line, the anode portion being connected to the power supply line, and the cathode portion being connected to the ground line, and a resistance portion provided at a predetermined location of a conductor extending from a branch node between the P-type and N-type MOS transistors to the power supply line via the P-type MOS transistor.

Protection circuit and semiconductor device

An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

Electrostatic discharge protection device for semiconductor integrated circuit method for producing the same and electrostatic discharge protection circuit using the same

A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Method for fabricating a LOCOS MOS device for ESD protection

Locos MOS device for ESD protection

An amplification type solid-state imaging device according to the present invention includes: a first gate region functioning as a photoelectric conversion region, a second gate region, and a source region, the first gate region surrounding the source region, and the second gate region adjoining the first gate region on a side opposite the source region, to discharge signal charge accumulated in the first gate region through the second gate region. The center of the source region is displaced from the center of a pixel.

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Kitakatsuragi-gun, Japan

Hidechika Kawazoe