Hitachi, Ltd.

Hideaki Yabe

Yoshio Oshima

Toru Ohtsuki

Sako Ishikawa

Masaharu Fukuta

Yasuhito Maejima

In the Internet having a plurality of autonomous systems interconnected, fast routing can be made. The autonomous systems constituting the Internet or the like are divided into groups. The border routers of one group share routing information of the group, and the border routers of another group share routing information of the group. Each border router has a unit for separating a desired one from the autonomous systems of a corresponding group or consolidating an autonomous system of another group into the corresponding group, so that the amount of the routing information held can be adapted to the processing ability of the border routers within that group.

Network structure method and route determination equipment

An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Apparatus for decimal multiplication

A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.

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Hadano, Japan

Hideaki Yabe