Fujitsu Corporation

Hideaki Tomatsuri

Hidetaka Ebeshu

Hiroyuki Kojima

Naoya Ishimura

Hiroyuki Fujiyama

Minoru Usui

Toru Hikichi

Noriaki Ono

Kenta Umehara

Hirotoshi Okada

An apparatus includes: a processor core to execute an instruction; a first cache to retain data used by the processor core; and a second cache to be coupled to the first cache, wherein the second cache includes a data-retaining circuit to include storage areas to retain data, an information-retaining circuit to retain management information that includes first state information for indicating a state of data retained in the data-retaining circuit, a state-determining circuit to determine, based on the management information, whether requested data that is requested with a read request from the first cache is retained in the data-retaining circuit, and an eviction-processing circuit to, where the state-determining circuit determines the requested data not to be retained in the data-retaining circuit with no enough space in the storage areas to store the requested data, evict data from the storage areas without issuing an eviction request based on the read request.

Operation processing device, information processing apparatus, and control method for operation processing device

An arithmetic processing device includes a plurality of core units, each including a plurality of cores each having a arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent connected to the cache memories provided respectively in the core units; and a memory access controller connected to the home agent and controls access to a main memory. The cache memories each includes a data memory having cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the cache blocks, and the home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared by cache memories, for each of the cache blocks in the cache memories provided respectively in each of the core units.

Arithmetic processing device and method for controlling arithmetic processing device

The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.

Cache system with limited number of tag memory accesses

A CPU performs read access to a plurality of resources. A plurality of buffers connect the plurality of resources to the CPU, respectively. The CPU causes one of the plurality of buffers connected to one of the plurality of resources to be in an active state so that the CPU can perform read access to the one of the plurality of resources via the one of the plurality of buffers, the one of the plurality of resources being given priority.

Semiconductor apparatus and read access method

Disclosed are a semiconductor device of which a block having a plurality of portions that operate based on a plurality of clocks can be designed and inspected easily, and a method of designing the semiconductor device. First and second clocks whose frequencies are mutually different are used to generate an enabling signal that is validated only during a short period including a transition edge of the second clock. The enabling signal and first clock are supplied to the second portion. The second portion synthesizes the enabling signal and first clock to substantially generate the second clock. Thus, the second portion is regarded as a portion that operates synchronously with the first clock.

Growing community of inventors

Narashino, Japan

Hideaki Tomatsuri