Sanyo Electric Co., Ltd.

Victor Company of Japan, Limited

Hideaki Sasaki

Yutaka Shimizu

Shigeru Sawada

Teruo Hotta

An offset adjusting circuit for an optical disc comprises a plurality of offset-adjustment differential operational amplifiers, each of the amplifiers having an input terminal to which an output signal of an optical pickup is input and another input terminal to which a control voltage is applied, an adding circuit that adds output signals of the offset-adjustment differential operational amplifiers, an A/D converter that outputs a digital signal based on an output signal of the adding circuit, and a control voltage adjuster that varies the control voltage applied to the offset-adjustment differential operational amplifiers based on the digital signal so as to remove an offset.

Offset adjusting circuit for optical disc and offset adjusting method

An offset adjusting circuit for an optical disc comprises an offset-adjustment differential operational amplifier having an input terminal to which an output signal of an optical pickup is input and the other input terminal to which a control voltage is applied, an A/D converter that outputs a digital signal based on an output signal of the offset-adjustment differential operational amplifier, and a control voltage adjuster that varies the control voltage applied to the offset-adjustment differential operational amplifier based on the digital signal so as to remove an offset.

An input video signal is written into alternate field memories M1 and M2, according to a timing clock from an input video clock generator. A display video signal is alternately read from those field memories, according to a timing clock from a display video clock generator. In switching a read memory, an address observation circuit judges whether or not a read/write address passes by a write/read address, referring to the condition of reading and writing operations. In this event, the circuit makes a judgement, based on the lag between a vertical synchronizing signals of an input video signal and of a display video signal, and a change of the lag with time. If it is judged that one address will pass by the other, the same read/write memory is again accessed for reading/writing. With this arrangement, there is provided a circuit having a relatively simple structure for preventing a match of read and write addresses.

Growing community of inventors

Gunma, Japan

Hideaki Sasaki