Oki Electric Industry Co., Ltd.

Hideaki Odagiri

Noriaki Takahashi

Naoya Kimura

Koji Takeshita

Yuichi Arata

Yuji Uyama

A digital matched filter stores a series of values of a digital input signal in a memory, compares each stored value with a corresponding value of a known code, and generates an analog comparison result signal for each comparison. The analog comparison result signals are combined to obtain an analog sum signal, which is then converted to a digital output signal. The digital output signal is obtained in real time, because there is little or no processing delay in combining the analog comparison result signals. The circuits that generate and combine the analog comparison result signals are similar to digital circuits, enabling the digital matched filter to be integrated easily with other digital signal-processing circuits.

Digital matched filter circuit employing analog summation

An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.

Associative memory for accomplishing longest coincidence data detection by two comparing operations

Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a synchronizing circuit, a conflict detector, and a conflict avoiding circuit. The circuitry detects a conflict with high reliability and facilitates design using a CAD (Computer Aided Design) tool.

Clock switching circuitry for avoiding conflict of data handling occuring in a memory

A CAM device has an HIT flag cell and a word select separation circuit, with data being stored in a plurality of CAM cells. The HIT flag cell then stores whether or not data stored in the CAM and inputted words (data) coincide. The word select separation circuit the detects the lowest address values corresponding to words within coinciding words and then sequentially resets HIT flag cells storing the coinciding of words.

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Chiba, Japan

Hideaki Odagiri