Kabushiki Kaisha Toshiba

Hideaki Nii

Mizuki Ono

Hiroshi Iwai

Masanobu Saito

Yukihiro Ushiku

Satoshi Matsuda

Yasushi Akasaka

Hisayo S Momose

Takashi Yoshitomi

Yasuhiro Katsumata

Shigeru Kawanaka

Takashi Yamada

Tsuneaki Fuse

Tomoaki Shino

Makoto Yoshimi

Kazumi Inoh

Sadayuki Yoshitomi

Claudio Fiegna

Tatsuya Ooguro

Mamoru Terauchi

Chihiro Yoshino

A method of manufacturing a semiconductor device is provided. The method includes providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type. An opening is formed penetrating the device isolation region and the embedded insulation layer and reaching the semiconductor substrate. A polysilicon is deposited on the SOI substrate and within the opening and providing a gate electrode and a substrate electrode of the MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into the gate electrode and the substrate electrode.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film. An element separating insulating film separates element area. A first gate insulating film is provided on the semiconductor layer in the element area. A gate electrode is provided on the first gate insulating film. Source/drain diffusion layers are formed in the semiconductor layer sandwiching a channel area under the gate electrode therebetween. A potential applying section inducing a leak current which controls the potential of the semiconductor layer comprises a second gate insulating film provided on the semiconductor layer in the element area and a conductive film provided on the second gate insulating film and connected to the gate electrode. The potential applying section is configured so that a leak current through the second gate insulating film is larger than a leak current through the first gate insulating film.

Semiconductor device formed in a semiconductor layer provided on an insulating film

A bipolar transistor has metal silicide as a base lead-out electrode instead of conventional polysilicon, and the metal silicide film extends to an edge of an etching stopper layer, to reduce an emitter resistance and restrain an occurrence of an emitter plug effect. Such bipolar transistor can be utilized in a CMOS semiconductor device. In this case, (1) commonly using a process of providing an active base region, a base lead-out electrode and a collector lead-out electrode of the bipolar transistor and a process of providing gate electrodes a MOS field effect transistor, (2) commonly using a process of adding a p-type impurity into the active base region and the base lead-out electrode and a process of executing an ion-implantation for providing high-concentration impurity diffused layers of pMOS transistors, (3) commonly using a process of providing an etching stopper layer and a process of providing side wall insulating films of gate electrodes, and (4) commonly using a silicidation process of the base lead-out electrode and the collector lead-out electrode and a silicidation process of electrodes of MOS transistors. In other embodiment of the bipolar transistor, a single insulating film exist between the base layer and the emitter electrode in the peripheral of the emitter opening. By this construction, the etching stopper film is not necessary resulting in reducing the base resistance.

Semiconductor device

A semiconductor device comprises an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulating layer on a first conductivity type semiconductor substrate; a MIS type field-effect transistor provided within a device region defined by isolating said mono-crystalline semiconductor layer with a device isolation region and having a gate electrode; an opening formed penetrating said device isolation region and said embedded insulating layer and reaching said semiconductor substrate; and a substrate electrode provided covering said opening and taken out up to the surface flush with said gate electrode. And a method of manufacturing a semiconductor device, comprises providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type; forming an opening penetrating said device isolation region and said embedded insulation layer and reaching said semiconductor substrate; depositing polysilicon on said SOI substrate and within said opening and providing a gate electrode and a substrate electrode of said MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into said gate electrode and said substrate electrode.

In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Lateral bipolar transistor formed on an insulating layer

In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.

Method for manufacturing a lateral bipolar transistor

The proposed semiconductor device can provide a capacitor having an excellent capacitance controllability thereof and a high reliability thereof. A method of manufacturing a semiconductor device comprises the steps of: forming a first insulating film on a semiconductor substrate on which a lower capacitor electrode has been formed; removing the first insulating film at a capacitor forming region on the lower capacitor electrode; forming a second insulating film on the semiconductor substrate; forming a conductive film on the formed second insulating film; patterning the conductive film and the second insulating film, to leave both the films at least at the capacitor forming region; patterning the first insulating film, to form a contact hole with the lower capacitor electrode at a region other than the capacitor forming region; and dry etching the lower capacitor electrode, to remove a natural oxide film formed at a bottom of the contact hole.

Method of manufacturing a semiconductor device

A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff &gt;0.69 x.sub.j -6.17.

MOSFET with solid phase diffusion source

A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

Semiconductor device having solid phase diffusion sources

A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

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Yokohama, Japan

Hideaki Nii