Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Hitachi Microcomputer Eng. Ltd.

Hitachi Vsli Engineering Corp.

Hitachi Microcomputer Hitachi, Ltd. & Engineering, Ltd.

Hideaki Nakamura

Osamu Minato

Yoshitaka Kinoshita

Yukio Kawashima

Nobuyuki Moriwaki

Makoto Saeki

Sho Yamamoto

Shigeru Honjo

Masaaki Kubotera

Yasuo Yoshitomi

Shuji Ikeda

Kunihiko Nishi

Katsuro Sasaki

Michio Tanimoto

Nobuyoshi Tanimura

Tokumasa Yasui

Kiyofumi Uchibori

Toshihiro Yasuhara

Katsuhiro Tabata

Kohji Yamasaki

Isao Akima

Souichi Kunito

Yasuhiro Yoshikawa

Toshio Nosaka

Between an external terminal and the gate of one of output MOSFETs whose source or drain is connected to the external terminal, there is connected a P-channel type first protective MOSFET whose gate is connected to a high voltage side power supply terminal and which has a channel length equal to or larger than that of the output MOSFET, or an N-channel type second protective MOSFET whose gate is connected to a low voltage side power supply terminal and which has a channel length equal to or larger then that of the output MOSFET. When the external terminal is discharged by device charge, one of the protective MOSFETs is turned on, and the charge on the gate side of the output MOSFET can be likewise released by device charge to prevent ESD (Electro-Static Discharge) breakdown.

Semiconductor device

Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Semiconductor integrated circuit device having a compact arrangement of

A package is provided for achieving higher packing density and higher circuit integration of memories, in particular, a structure is provided having a plurality of thin, surface mount packages which are stacked up. Each of the laminated packages includes a semiconductor pellet, leads fixed to the front surface of the pellet, a radiating plate fixed to the rear surface of the same, and a resin mold member. To achieve a stabilized laminated structure, the mold member is shaped into a convex form on the front side of the pellet and into a concave form on the rear side of the same, so that the concave portion of one package can engage with the convex portion of another package.

Semiconductor device and an electronic device with the semiconductor

In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.

High speed semiconductor memory having a direct-bypass signal path

An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

MOS static type RAM having a variable load

An MOS static type RAM has a memory cell array comprising a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.

In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.

Static memory

Growing community of inventors

Kodaira, Japan

Hideaki Nakamura