Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Hideaki Nagaoka

Tomohisa Wada

Motoi Ashida

Kazuhito Tsutsumi

Kiyoyasu Akai

Yoshikazu Kamitani

Eiji Hamasuna

Yoshiyuki Haraguti

A semiconductor memory device is provided including plural memory cells and capable of a dual port access. In the memory device the memory cell is composed with two driver transistors , two load transistors , and two access transistors , and in the data read, the word line makes the access transistors conductive to read out data held in the driver transistors to a pair of the bit lines, and in the data write, the load transistor control line makes the load transistors conductive to write data into the driver transistors from a pair of the memory cell VCC lines.

Semiconductor memory device with dual port memory cells

The number of apparently independently operating memory sets can be changed by providing the same number of address setting circuits as that of memory cell arrays. Since the number of mounted address setting circuits increases compared with a case where the number of memory sets is fixed, the problem arises that the layout area in a semiconductor memory device increases. However, by providing a switching circuit for switching the correspondence relationship between memory cell arrays and address setting circuits in response to a signal selecting the number of memory sets, a semiconductor memory device capable of changing the number of memory sets which seemingly independently operate without providing the same number of address setting circuits as that of memory cell arrays.

Semiconductor memory device

A dummy pattern for use in a chemical mechanical polishing (CMP) process is disposed in a field dummy region within a p well region, isolated by an isolating insulating film, wherein the p well region has a potential fixed by a ground electrode. The dummy pattern includes a gate insulating film dummy pattern and a gate electrode dummy pattern, formed in the same layers as a gate insulating film and a gate electrode, respectively, of an NMOS transistor. The gate electrode dummy pattern is connected with a contact plug, which in turn is connected with a power supply electrode (Vcc) interconnection line. Thus, a decoupling condenser, formed of the field dummy region within the p well, the gate insulating film dummy pattern and the gate electrode dummy pattern by utilizing the dummy patterns for use in the CMP process, is connected in parallel with a primary electronic circuit. As a result, a semiconductor device is obtained which operates at a low voltage with suppressed electromagnetic interference (EMI), without increasing an area occupied by the semiconductor device.

Semiconductor device provided with on-chip decoupling condenser utilizing CMP dummy patterns

A memory cell power supply line is provided to supply a ground potential corresponding to each column in a regular memory cell array. Among fuse elements, the fuse element corresponding to the memory cell column that is to be subjected to redundancy replacement is decoupled, whereby supply of the ground potential to the regular memory cell column to be replaced is suppressed.

Static type semiconductor memory device that can suppress standby current

A memory cell power supply circuit includes: a memory cell power supply PMOS transistor connected between a power supply node and a power supply potential, a diode-connected transistor provided between a gate of the memory cell power supply transistor and the power supply potential, and a resistor provided between the gate of the memory cell power supply transistor and a ground potential. During a writing operation when a value of current flowing to the memory cell is high, if the power supply potential increases, a cell power supply potential down-converted by a greater amount is supplied to the memory cell.

Static semiconductor memory device with expanded operating voltage range

In an SRAM, a breaking circuit includes a P channel MOS transistor connected between the source of an N channel MOS transistor, which forms a bit line load, and one end of a bit line, and an inverter to supply the gate of the P channel MOS transistor with an inverted signal of a signal which appears at the one end of the bit line. If the bit line is short-circuited with a line of a ground potential and is defective, the P channel MOS transistor is rendered non-conductive, thereby preventing current leakage from a line of a power supply potential through the defective bit line to the ground potential line. Therefore, current consumption is reduced.

Static type semiconductor memory device for lower current consumption

A pair of dummy signal lines transmitting dummy signals, complementary to and synchronized with a normal signal, are arranged to form a set together with a normal transfer line transmitting the normal signal. In a device on a receiving side, one of the dummy signal lines is selected and coupled in accordance with the logic level of the normal signal, whereby two ringings occur in the opposite phases on the receiving side, and cancel each other so that ringing of the normal signal can be suppressed. An input/output interface, which can transfer a signal having a short level transition time without causing ringing, can be provided.

Semiconductor device allowing fast signal transfer and system employing the same

A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.

Static semiconductor memory device

In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor. A gate circuit having a small dependency of an input/output characteristics on the power supply voltage is implemented without increasing the power consumption.

Semiconductor gate circuit having reduced dependency of input/output

Memory blocks having word lines driven into selected states independently of each other are provided in correspondence to data input/output bits respectively. Each memory cell includes a bipolar transistor and a MOS transistor. In each memory block, a current flows to a bit line only of a selected column, and a 1-bit memory cell is accessed therein. Thus, sense amplifiers and write drivers have only to be provided in numbers corresponding to that of the data bits, whereby the circuit occupying area as well as current consumption are reduced.

Static semiconductor memory device with reduced power consumption, chip

A semiconductor memory device comprises first and second data buses. An output drive circuit adjusts the potentials at the first and second data buses in response to an internal read signal read from a memory cell. The gates of a PMOS transistor and an NMOS transistor forming an output stage corresponding to an output final stage are connected to ends of the first and second data buses, respectively. The potential of an output signal derived from the output stage loosely transits with a value decided by the capacitances of the first and second data buses. Thus, through rate control of the output signal can be implemented without reducing current drivability of the MOS transistors forming the output final stage.

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Hyogo, Japan

Hideaki Nagaoka