Hitachi, Ltd.

Hideaki Monji

Yuusaku Kiyota

Tomohiro Yoshihara

Takashi Nagao

Tomoyuki Kamazuka

Shumpei Morita

Yoshiaki Eguchi

A storage system that can achieve a cryptographic operation circuit that supports multiple types of cryptographic operation formats. The cryptographic operation circuit is provided that encrypts data according to the format determined by the processor based on a request by the host terminal for writing the data into the storage device, and decrypts the encrypted data on the data stored in the storage device according to the format determined by the processor based on a request by the host terminal for reading the data from the storage device.

Storage system and cryptographic operation method

A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.

Storage system and input and output control method

Encryption is enabled at a low load in a storage system. An encryption processing deviceuses, as an expectation value for key validation, a value that is uniquely identified from a storage location address of encrypted text data in a storage drive. The encryption processing deviceencrypts the expectation value and plain text data, respectively, using a same encryption key, substitutes a DIF according to the encrypted text data obtained by encrypting the plain text data, and stores the encrypted expectation value in the substituted DIF. Upon receiving a read request of the encrypted text data, the encryption processing devicedecrypts the encrypted expectation value stored in the substituted DIF using a decryption key, and validates whether the encryption key and the decryption key are properly corresponding by comparing the decrypted expectation value and the expectation value identified from the address at the time of reading.

Storage system and encryption processing method

In a cryptographic apparatus, a cryptographic module executes first assurance check processing, which is processing for satisfying a predetermined certification requirement on image data of first software, and also executes second assurance check processing, which is processing for satisfying the above predetermined certification requirement on a verification target, which is at least part of image data of second software, and on which verification for satisfying the predetermined certification requirement is not performed by a device.

Cryptographic apparatus and self-test method of cryptographic apparatus

A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.

Data transfer system

Starting a host computer and a high-speed data transfer achieved by NVMe are both realized. When the host computer is started and a command for instructing to read an OS in accordance with a specific protocol is issued from the host computer via a host-side bus to a specific function from among a plurality of functions, an interface device issues to a controller a request for instructing to read the OS and transfers the OS read by the controller to the host computer. When an NVMe command for instructing an I/O for the controller in accordance with an NVMe protocol is issued from the host computer via the host-side bus to an NVMe function from among a plurality of functions after the host computer is started, the interface device issues to the controller an I/O request based on the NVMe command.

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Tokyo, Japan

Hideaki Monji