Fujitsu Corporation

Hideaki Mochizuki

Hiroshi Murakawa

Ritsuko Isonuma

Kazuhisa Kada

Shigehisa Sakahara

Hidenori Kiuchi

Ritsuko Ohkura

Ritsuko Okura

Yuji Obana

Hiroshi Yoshida

Kazuo Takatsu

Kanta Yamamoto

Hideo Abe

Masahiro Shinbashi

Junichi Ishiwatari

Akihiko Oka

Kimio Uekama

Hideaki Tazawa

Ichiro Yokokura

Koji Iwamoto

In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of dataclock prior to and a head bit of dataclock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.

Jitter correction method and circuit

In a method and a circuit for timing pulse generation, a frame pulse of a corresponding system is masked when an alarm signal of either a working system or a protection system is received, a monitoring window which indicates an absorbable range of delay time difference between the frame pulses is generated upon an arrival of the frame pulse of the system selected by a switching signal, when the alarm signal of a system not selected is generated upon selection of the switching signal. Alternatively, a request signal for regenerating the monitoring window which indicates an absorbable range of delay time difference between the frame pulses is provided upon an arrival of the frame pulse of the system selected by the switching signal, when a slip signal is generated upon selection of the switching signal. The monitoring window is generated around the frame pulse selected by the switching signal when the monitoring window generation request signal is received, a read timing pulse common to memories of both systems is generated at a predetermined timing position, and the monitoring window is regenerated when the selected frame pulse deviates from the monitoring window. Alternatively, a correction signal including a number and a direction of bits when a reference timing pulse not selected deviates from the monitoring window is generated to be transmitted, the correction signal is extracted from a main signal received, and a position of the reference timing pulse of the protection system is corrected based on the correction signal, when the protection system is presently selected.

Method and circuit for timing pulse generation

A transmission device which cross connects channels on a synchronous multiplex transmission network which forms a ring, and which performs restoration of communication by looping back signals in a protection path when a failure occurs includes a memory area which stores information for determining whether an alarm indication signal needs to be inserted in a channel or not, wherein the size of the memory area corresponds to the number of channels targeted for the restoration, and a part which inserts said alarm indication signal in a channel by switching results of the determination according to predetermined information. Further, the transmission device may switch and recover a path without skipping an event which arises between polling accesses by a CPU of said transmission device. Furthermore, the transmission device may include a part, provided in each interface part, which performs phase adjusting of channel signals.

Transmission device

A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

Digital phase locked circuit capable of dealing with input clock signal provided in burst fashion

There is disclosed a transmission device performing NUT setting and its establishment efficiently and precisely. A setting information relay unit relays setting information that places a specific channel out of a channel used for restoration. A channel establishment unit determines, by referring to the setting information, whether a channel of interest should be placed out of a channel for restoration and establish the channel. A route switch control unit recognizes a section in which the channel that is not used for restoration has been established and a fault bypass control condition at the time of occurrence of a fault and performs a route switching control based on a result of recognition.

A fixed length data processing apparatus has a registration holding unit holding registration information necessary to identify fixed length data that is an object of a processing commonly to transmission routes, and a data processing unit identifying whether received fixed length data is fixed length data that is an object of the processing or not on the basis of at least the registration information in the registration information holding unit to perform a data processing for fault management in the asynchronous communication on the basis of the fixed length data when identifying that the fixed length data is fixed length data that is an object of a processing correspondingly to the transmission route, thereby holding a large volume of information efficiently for identifying fixed length data to process fixed length data with a simple structure.

Fixed length data processing apparatus

A transmission device far efficient synchronous multiplexing control for downsizing and reducing power consumption. A count control performs channel management control on a cross-connect basis using count control of channels of high-bit-rate and low-bit-rare multiplexing unit signals. A part which detects a head position of path information based on pointer value. A part which performs clock exchange with respect to valid path information indicated by head position. A part which generates a write count value, a read count value, and adds a pointer to the valid path information read. A cross-connect circuit uses two-plane memory, and cross-connects a signal with the pointer being replaced by memory reading based on memory switch information.

SONET/SDH transmission control device

A transmitting apparatus for cross connecting and transmitting main signals which enter via ring-configured transmission lines to which working and protection channels have been assigned in first and second directions, and rescuing a main signal by looping back the main signal in the opposite direction using the protection channel when a transmission line fails. Storing non-rescue information which indicates whether each channel that is the object of rescue by loop-back is a non-rescue channel. Determining whether a failure for which rescue is impossible has occurred in each channel, which is the object of rescue, other than a non-rescue channel. On the basis of main-signal cross-connect information, interchanging a result of discrimination of each channel and inserting the interchanged result of discrimination in the main signal of the corresponding channel after cross connect.

Transmitting apparatus

Retainment of alarm events during wait restore (WTR) cycle of channel restoration and squelch table with reduced memory area

A fixed length data processing apparatus has a data processing unit receiving at least fixed length data to perform a desired data processing on the fixed length data, and an operation state monitoring process unit performing a monitoring process to monitor an operation state of an asynchronous communication on the basis of the fixed length data received by said data processing unit, thereby detecting loss or misinsertion of fixed length data such as an ATM cell or the like and monitoring a flow state in a transmission system having a high transmission rate.

An ATM device includes an extractor which extracts a cell related to a performance monitor process for an ATM layer, a processing unit executing the performance monitor process, a memory which stores information concerning the performance monitor process, and a decision making unit which compares the information stored in the memory with cell information of the cell extracted by the extractor and which makes a decision as to whether the cell extracted by the extractor should be supplied to the process unit.

ATM device

An add drop multiplexing (ADM) apparatus has a simple and compact structure. The ADM apparatus has high-order interfaces connected to a high-order network, path setting units each for setting a path for a signal according to path data and inserting or dropping the signal to or from the high-order network, a first path protection switch for selecting one of the signals dropped by the path setting units, low-order interfaces each for receiving the selected signal and transmitting the same to a low-order network, and a second path protection switch for receiving low-order signals from the low-order interfaces and transferring one of them to the path setting units so that the path setting units may insert the signal into the high-order network.

Add-drop multiplexing apparatus

An OEM processing device for supporting operations, administration, and maintenance (OAM) in an ATM network, whose control circuit has a simplified configuration that avoids duplexity of common functions, thus realizing reduced size and less power consumption. A VPI/VCI extractor extracts VPI/VCI from each incoming ATM cell, while an alarm detector detects a physical layer alarm. An entry data memory stores a plurality of VPIs/VCIs that have been previously registered. When the extracted VPI/VCI is found in the registered VPIs/VCIs in the entry data memory, a VPI/VCI coincidence signal will be generated. When a physical layer alarm is detected by the alarm detector, all the relevant VPIs related to the detected alarm will be generated by using the same entry data memory. A VP-AIS cell generator then produces VP-AIS cells corresponding to the generated VPIs and inserts them into the current ATM cell stream.

OAM processing device in an ATM network

An add-drop multiplexer contains a partial drop unit and a partial add unit. The partial drop unit selects a number n of first signal(s) of n channel(s) among a number N of first signals of N channels, which are received from a first transmission line, and transmits the n first signal(s) of n channel(s) on at least one second transmission line, where N and n are integers satisfying N&gt;n&gt;0. The partial add unit receives n second signal(s) of n channel(s) from at least one third transmission line, and a number (N-n) of first signal(s) of (N-n) channel(s) among the N first signals of the N channels, which are not selected by the partial drop unit, and transmits on the first transmission line the n second signal(s) of n channel(s) and the (N-n) first signal(s) of (N-n) channel(s) as N third signals of N channels.

Growing community of inventors

Kawasaki, Japan

Hideaki Mochizuki