Nippon Telegraph and Telephone Corporation

Hideaki Matsuzaki

Masahiro Nada

Hiroki Sugiyama

Fumito Nakajima

Takuya Hoshi

Yuki Yoshiya

Yuki Yamada

Takuya Tsutsumi

Yoshifumi Muramoto

Hiroyuki Ishii

Naoki Fujiwara

Shinji Matsuo

Takashi Yamada

Kengo Horikoshi

Takahiko Shindo

Kimikazu Sano

Kenji Kurishima

Minoru Ida

Yuta Shiratori

Kunihiro Arai

Miwa Muto

A gate electrode includes a main portion formed of a gate electrode material, and a gate electrode barrier layer disposed between the main portion and a barrier layer and formed of a conductive material that prevents the gate electrode material from diffusing into the barrier layer. A surface of the main portion in a region above a first insulating layer faces a periphery without a layer of the conductive material being formed.

Field-effect transistor and method for manufacturing the same

An emitter contact layer, an emitter layer, a base layer, a p-type base layer, a collector layer, and a sub-collector layer are crystal-grown over a first substrate in this order with the main surface as the Group III polar surface. The emitter contact layer includes a nitride semiconductor that is made n-type at a relatively high concentration. The emitter layer includes a nitride semiconductor having a bandgap larger than that of the nitride semiconductor constituting the emitter contact layer. The base layer includes an undoped nitride semiconductor having a bandgap smaller than that of the nitride semiconductor constituting the emitter layer. The p-type base layer includes the same nitride semiconductor as the base layer and made p-type.

Heterojunction bipolar transistor and manufacturing method of the same

A structure includes an insulating layer on a semiconductor substrate, and a first through-hole and a second through-hole formed in the insulating layer. The second through-hole is formed in the insulating layer at a set distance from the first through-hole. The structure also includes a first electrode portion and a second electrode portion. The first electrode portion is formed by filling the first through-hole. The first electrode portion includes a probing pad on the insulating layer. The probing pad is wider than an opening area of the first through-hole. The second electrode portion is formed by filling the second through-hole. The second electrode portion includes a probing pad on the insulating layer. The probing pad is wider than an opening area of the second through-hole.

Inspection structure and inspection method

A first semiconductor layer, a second semiconductor layer, a channel layer, a barrier layer, and a third semiconductor layer are crystal-grown in this order on a first substrate in the +c axis direction, a second substrate is bonded to the side of the barrier layer of the first substrate, and after that, the first substrate is removed, and the first semiconductor layer is selectively thermally decomposed by heating.

Method for fabricating field-effect transistor

A first regrowth layer and a second regrowth layer comprising GaAs having high resistance are regrown on a surface of an etching stop layer exposed to the bottom of a first groove and a second groove, and then n-type InGaAs is regrown on the first regrowth layer and the second regrowth layer, whereby a source region and a drain region configured to make contact with a channel layer are formed in the first groove and the second groove respectively.

Transistor manufacturing method

A gate opening portion, which is disposed within a recess formation region in a state where the distance from a drain electrode is greater than the distance from a source electrode, is formed in an insulating layer. The gate opening portion is a stripe-shaped opening that extends in a gate width direction. Also, a plurality of asymmetric recess-forming opening portions are formed, arranged in a row in the gate width direction between the gate opening portion and the drain electrode within the recess formation region in the insulating layer. In this step, asymmetric recess-forming opening portions are formed whose opening size in the gate length direction is greater than the opening size in the gate width direction.

Field-effect transistor and manufacturing method therefor

A light-receiving device includes: a plurality of light-receiving elements arranged in a row on a main surface of a substrate and a first reflection surface and a second reflection surface formed on the substrate to extend in the arrangement direction with the row of the plurality of light-receiving elements interposed therebetween. Each of the first reflection surface and the second reflection surface includes an inclined surface forming one flat surface formed from a main surface of the substrate on which each light-receiving element is formed to a back surface side of the substrate.

Photoreceiver and optical receiver having an inclined surface

A substrate, a first n-type contact layer, a buffer layer, a multiplication layer, an electric field control layer, an absorption layer, and a p-type contact layer are provided. An electrically conductive layer is formed in a central portion of the buffer layer. The substrate is made of a semiconductor having thermal conductivity higher than that of InP, such as SiC, and the first n-type contact layer is made of the same semiconductor as that of the substrate but having n-type conductivity. An n electrode is formed over the first n-type contact layer via a second n-type contact layer.

Avalanche photodiode and method for manufacturing same

A gate opening, a plurality of first openings arranged in a gate widthwise direction and having a reed shape, a second opening connecting the adjacent first openings, and a third opening connected to a side away from the arrangement of the first opening at an end of the arrangement are formed in an insulation layer. An ohmic cap layer is etched via the openings to form an asymmetric recess region.

Field effect transistor and method for manufacturing the same

A first barrier layer, a channel layer, a second barrier layer, and a first bonding layer made of high-resistance AlGaN doped with Fe are formed on a first substrate. Thereafter, the first substrate and the second substrate are pasted in a state where the first bonding layer and a second bonding layer made of high-resistance GaN doped with Fe are opposed to each other.

Method for manufacturing transistor

A method for manufacturing a monolithically integrated semiconductor optical integrated element comprising a DFB laser, an EA modulator, and a SOA disposed in a light emitting direction, comprising the step of forming a semiconductor wafer on which the elements are two-dimensionally arrayed and aligned the optical axes; cleaving the semiconductor wafer along a plane orthogonal to the light emitting direction to form a semiconductor bar including a plurality of the elements arranged one-dimensionally along a direction orthogonal to the light emitting direction such that the elements adjacent to each other share an identical cleavage end face as a light emission surface; inspecting the semiconductor bar by driving the SOA and the DFB laser through a connection wiring part together; and separating out the semiconductor bar after the inspection to cut the connection wiring part connecting the electrode of the SOA and the DFB laser to isolate from each other.

Semiconductor integrated optics element and production method therefor

A first signal electrode and a second signal electrode are connected by a first wire, a first ground electrode and a fourth ground electrode are connected by a second wire, and a second ground electrode and a third ground electrode are connected by a third wire. The second wire and the third wire cross at only one position above the first wire.

Wire bonding structure

An n-type semiconductor layer (), a multiplication layer (), an electric field control layer (), a light absorption layer (), and a p-type semiconductor layer () are formed on a growth substrate (), and the p-type semiconductor layer () is adhered on a transfer substrate (). After that, the growth substrate () is removed, and the n-type semiconductor layer () is processed to have an area smaller than that of the multiplication layer ().

Avalanche photodiode and method of manufacturing the same

An optical waveguide integrated light receiving element includes an optical waveguide () arranged on a side of a second contact layer () opposite to a side where a light absorption layer () is arranged, having a waveguide direction parallel to a plane of the light absorption layer (), and optically coupled with the second contact layer (). The second contact layer () has, in a planar view, a size of an area smaller than that of the light absorption layer () and arranged inside the light absorption layer ().

Optical waveguide integrated light receiving element and method of manufacturing the same

To obtain high linearity without sacrificing light-receiving sensitivity and a high speed, an avalanche photodiode includes an avalanche layer () formed on a first light absorption layer (), an n-field control layer () formed on the avalanche layer (), and a second light absorption layer () formed on the field control layer (). If a reverse bias voltage is applied, a donor impurity in the field control layer () ionizes, and a high electric field is induced in the avalanche layer (). The n-type doping amount in the field control layer () is set such that the impurity concentration in the second light absorption layer () sufficiently depletes at the time of reverse bias application.

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Tokyo, Japan

Hideaki Matsuzaki