Oki Electric Industry Co., Ltd.

Hideaki Matsuhashi

Toshiyuki Nakamura

Jun Kanamori

Yoshihiro Koga

Yoko Kajita

A method of manufacturing a capacitor having a couple of electrodes with a dielectric placed therebetween. At least one of the electrodes is made of copper, and barriers for preventing the diffusion of copper into the dielectric are provided between the dielectric and the copper electrode, respectively.

Method of manufacturing a capacitor with copper electrodes and diffusion barriers

A capacitor has a couple of electrodes with a dielectric placed therebetween. At least one of the electrodes is made of copper, and barriers for preventing the diffusion of copper into the dielectric are provided between the dielectric and the copper electrode, respectively.

Capacitor having copper electrodes and diffusion barrier layers

A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.

Method for manufacturing field effect transistor

A lower buried oxide film, a stress-relief film, an upper buried oxide film, and an SOI film are formed over a semiconductor substrate in this order. The thermal expansion coefficient of the stress-relief film is greater than the thermal expansion coefficient of the upper buried oxide film. The stress-relief film desirably has a thermal expansion coefficient equal to or greater than the thermal expansion coefficient of the SOI film. For example, it is formed of a silicon film, or of a composite film laminating a silicon film, a germanium film disposed thereon, and a silicon film disposed thereon. Accordingly, a semiconductor device having an SOI MOSFET is to be provided, which has excellent characteristics such as low parasitic capacitance and a small S value and is hardly affected by the stress generated by the difference between thermal expansion coefficients of the buried oxide film and the SOI film.

Semiconductor device formed on an SOI structure with a stress-relief layer

A capacitor has a coupled of electrodes with a dielectric placed therebetween. At least one of the electrodes is made of copper, and barriers for preventing the diffusion of copper into the dielectric are provided between the dielectric and the copper electrodes, respectively.

Capacitor and a manufacturing process therefor

An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1&times;10 to 5&times;10 cm . Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.

MOSFET fabrication method

A fabrication method for fabricating a dual-gate CMOSFET on a semiconductor substrate according to the present invention includes: implanting ions of N-type impurity for forming a deep junction source and drain in a first region on the semiconductor substrate where an NMOSFET is to be formed; performing a first annealing process for activating the N-type impurity; implanting ions of P-type impurity for forming a deep junction source and drain in a second region on the semiconductor substrate where a PMOSFET is to be formed; and performing a second annealing process for activating the P-type impurity. By performing the above processes in that order, the N-type impurity ions in the N polysilicon gate electrode of the NMOSFET are sufficiently activated, thus preventing the problem of depletion. Also, fluctuation of a threshold voltage because of penetration of the P-type impurity ions in the gate electrode of the PMOSFET can be prevented in the PMOSFET.

Fabrication method of a dual-gate CMOSFET

In a method of depositing a tungsten film on a gate oxide by means of laser CVD, using WF.sub.6 and H.sub.2 as raw material gases, the H.sub.2 /WF.sub.6 flow ratio lies within the range 10-100, and the volumeric flow rate of the WF.sub.6, which is defined as the ratio of the flow rate of WF.sub.6 to the total pressure, lies within the range 0.04-0.01 sccm/Pa, so that the supply of WF.sub.6 determines the deposition rate of the W film, whereby a low stress W film is obtained. Accordingly, peeling of the W film at the interface with the SiO.sub.2 film and cracks can be avoided.

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Tokyo, Japan

Hideaki Matsuhashi