Kabushiki Kaisha Toshiba

Hideaki Maekawa

Toshifumi Minami

Yuuichi Tatsumi

Takafumi Ikeda

Takahito Nakazawa

A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

Semiconductor memory device and method of fabricating the same

A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.

Semiconductor device having a protection pattern with two element separation regions

In the semiconductor of the present invention, the first pair of pad lines consisting of a plurality of pads are arranged on the bottom portion of the recess portion of the enclosure, the recess portion being made at the center portion of the enclosure by the counterboring process to have a predetermined depth. At approximately center of the recess portion, a suction opening is made so as to suck the potting material from outside. In the recess portion of the enclosure, the semiconductor chip is supported. The semiconductor chip has the second pair of pad lines arranged to oppose to the first pair of pad lines and electrically connected to the first pair of pad lines respectively. The potting material is poured into the recess portion so as to completely cover the semiconductor chip. At the same time, the potting material is sucked from the suction opening.

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Yokohama, Japan

Hideaki Maekawa