Sony Corporation

Hideaki Kuroda

Akira Nakagawara

Yoshiaki Hagiwara

Michitaka Kubota

Hideharu Nakajima

Keiichi Ono

A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.

Semiconductor device and method of manufacturing the same

A semiconductor device including a transistor formed on a first surface of a silicon layer; a first insulating film formed on the first surface of said silicon layer and covering said transistor; a wiring section formed in the first insulating film and electrically connected to the transistor; a supporting substrate formed on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; and an adjusting insulating film for adjusting a threshold voltage of said transistor, the adjusting insulating film being formed on a second surface of said silicon layer opposing the first surface of said silicon layer. Some embodiments may include a probing electrode electrically connected to the transistor and an opening in the silicon layer for exposing the probing electrode.

Semiconductor device manufacturing method and semiconductor device

A semiconductor device includes: a semiconductor layer; an element isolation region formed in the semiconductor layer for separation between a memory element part and a logic element part; first and second field-effect transistors formed in the memory element part and having first and second gate electrodes on a first surface side of the semiconductor layer and a second surface side opposite to the first surface, respectively, and having a source and drain region in common with each other; a third field-effect transistor formed in the logic element part and having a third gate electrode on the second surface side; and first and second insulating films formed on the semiconductor layer to cover the first field-effect transistor and the second and third field-effect transistors, respectively. The first field-effect transistor and the second field-effect transistor are fully-depleted field-effect transistors. The first gate electrode and the second gate electrode are electrically connected.

Memory element with small threshold voltage variance and high-speed logic element with low power consumption

A semiconductor device manufacturing method includes the steps of: forming a transistor on a surface side of a silicon layer of a silicon-on-insulator substrate, the silicon-on-insulator substrate being formed by laminating a substrate, an insulating layer, and the silicon layer; forming a first insulating film covering the transistor and a wiring section including a part electrically connected to the transistor on the silicon-on-insulator substrate; measuring a threshold voltage of the transistor through the wiring section; forming a supporting substrate on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; removing at least a part of the substrate and the insulating layer on a back side of the silicon-on-insulator substrate; and adjusting the threshold voltage of the transistor on a basis of the measured threshold voltage.

A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an opening reaching the impurity region, and a second insulating film and a second semiconductor layer of a second conductivity type stacked in the opening.

One time programmable semiconductor nonvolatile memory device and method for production of same

Semiconductor device having a selectively deposited conductive layer

A semiconductor device comprising a first connecting plug for bit contact and a second connecting plug for storage node contact buried in a first inter-layer insulating layer covering the transistor and projecting from the transistor. The bit line is buried in a second inter-layer insulating layer and connected to the first connecting plug. The electrode of the storage node is partially buried in the second inter-layer insulating layer, connected on the second connecting plug, and projected above the second inter-layer insulating layer.

A semiconductor device wherein in formation of the wiring connection, an opening is made up to the middle of the insulating film, a side wall is formed, a burying wiring with the lower portion is arranged, a pad is formed, and a pad is formed in a polyplug contact without a masking step. Further, a conductive material is filled in the hole in the insulating film, a hole is opened in this material, a side wall is formed on the inner wall, a shrunken contact is opened by using this as a mask, and the conductive material is filled.

An LDD-structured field-effect semiconductor device that can eliminate fluctuations in the threshold voltage caused by variations in the position of higher-density diffusion layers, thereby suppressing variations in the threshold voltage to a lower level. The junction depth of each of the lower-density diffusion layers in contact with a substrate is greater than the depth of a depletion layer at the place corresponding to a portion of the channel region contacting the source region. This prevents a change in the positional relationship between diffusion layers serving as, what are referred to as 'pocket layers', and the depletion layer adjacent to the source, even though the position of the higher-density diffusion layers is varied in the longitudinal direction of the channel due to variations in the width of a spacer. Thus, there are no fluctuations in the quantity of impurities contained in the pocket layers within the depletion layer adjacent to the source, which would otherwise influence the threshold voltage.

LDD buried channel field effect semiconductor device and manufacturing

An impurity for adjusting a threshold voltage is ion-implanted using, as masks, a resist for forming P.sup.- -type diffusion layers, a resist for forming N.sup.+ -type diffusion layers and N-type diffusion layers and a resist for forming P.sup.+ -type diffusion layers and N-type diffusion layers. For this reason, a semiconductor device including first to third N-channel transistors and first and second P-channel transistors, all of which respectively have different threshold voltages, can be manufactured without using an additional resist except for the above resists. Therefore, an operating margin at a low voltage can be increased and data retention characteristics can be improved in a memory without causing an increase in cost, an increase in power consumption and the like.

Semiconductor device having various threshold voltages and manufacturing

Disclosed is a MOS transistor and a fabrication process for the MOS transistor. Each gate electrode pattern made of silicon is formed on a gate oxide film formed on a silicon base body. An impurity is doped in the silicon base body using the gate electrode patterns as a mask, followed by activation of the impurity thus doped, to form diffusion layers in a surface layer of the silicon base body. An interlayer insulating film is formed in such a manner as to cover the gate electrode patterns. An upper portion of the interlayer insulating film is removed to expose the upper portion of each gate electrode pattern. The gate electrode pattern thus exposed is removed by selective etching. After that, a recessed portion formed by removal of each gate electrode pattern is embedded with a metal material, to form a CMOS transistor.

MOS transistor and fabrication process for the same

In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO.sub.2 films 16 and 34 covering the tungsten polycide layer 35 provided as the gate electrode and by the SiO.sub.2 film 12 in the device isolating region, and the titanium polycide layer 44 is brought into contact with the entire surface of the diffusion layer 17 while being extended on the SiO.sub.2 films 12 an d 16. Accordingly, a large allowance in aligning the contact hole 25 with respect to the titanium polycide layer 44 can be assured to make the contact compensation ion implantation unnecessary.

Growing community of inventors

Kanagawa, Japan

Hideaki Kuroda