Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Hideaki Kosaka

Tetsuro Shida

Kihei Ido

Masako Yamada

Masayuki Ohta

Kenji Tsunashima

Kenji Maeno

Toshimitsu Sato

Midori Sakaguchi

The transmission terminal in a wireless communication system includes: a communication unit for intermittently transmitting a radio signal; a transmission-side beacon reception unit; a beacon analysis unit for analyzing the received beacon signal; and a transmission output level change unit for estimating an emission time period of a beacon signal to be received by the transmission-side beacon reception unit on the basis of the beacon period information and the beacon reception time information, thereby obtaining an estimated emission time period; wherein the transmission output level change unit instructs the transmission-side communication unit to transmit the radio signal having a raised transmission output level during at least the estimated emission time period, the raised transmission output level being higher than a transmission output level during a time period other than at least the estimated emission time period.

Wireless communication system, transmission terminal, reception terminal, and transmission method

An MPEG recording and playback device is provided which can provide pertinent information on a program being played back to viewers at least in certain forms with certainty, thereby facilitating viewers' convenience. In this MPEG recording and playback device, during recording of MPEG data, a program information collecting unit () collects pertinent information on program responsive to an input path of the MPEG data by changing a method of collection, and the pertinent information on program is recorded in a different location of a track from that for the MPEG data. During playback, recorded pertinent information on program is outputted after being superimposed on an MPEG decoded analog image signal.

MPEG recording and playback device

An MPEG data recorder comprises an interface means for receiving a data packet from a digital transmission line transmitting MPEG data in real time, and extracting a predetermined MPEG data from a received packet to output it as a data signal; a data rate detector means for determining a data rate of MPEG data based on a valid data period, during which the data signal is outputted from the interface means; and a recording mode selector means for selecting a recording mode based on the determined data rate. According to such a configuration, the data rate of MPEG data can be detected without a necessity of analyzing the MPEG data, which would require an MPEG system layer decoder, and thereby an MPEG data recorder can be obtained, in which MPEG data are recorded efficiently in a proper recording mode, with a simplified circuit configuration.

MPEG data recorder including an MPEG data rate detector

An MPEG data recording apparatus stands by while inputting MPEG data output from an IEEE 1394 interface () to an FIFO buffer section () and starts to record the MPEG data in the FIFO buffer section () at the time of a recording start operation of a user, and records all the MPEG data which have already been input into the FIFO buffer section () at the time of a recording stop operation of the user and then stops the recording operation. Obtained is the MPEG data recording apparatus capable of quickly responding to the recording start operation and the recording stop operation of the user when recording the MPEG data input through the IEEE 1394 interface by the recording operation of the user.

MPEG data recording apparatus having IEEE 1394 interface

A slow decode control part divides a reference clock generated by a VCXO at a ratio of a slow speed to a normal speed. An STC circuit counts the divided clock. A time for starting decoding by an MPEG video decode part is decided by comparing a DTS included in MPEG data with the count of the STC circuit. A display time determination part determines a timing for outputting decoded data by comparing a PTS included in the MPEG data with the count of the STC circuit. Decoded data temporarily held in a frame buffer is output in response to a signal generated in a determination part on the basis of frame frequency information included in the MPEG data. Thus, slow reproduction is implemented with a high degree of freedom not limited to an integer-fractional speed without requiring a complicated circuit structure.

Decoder and reproducing unit

A data conversion method, wherein a sequence of first r-bit datawords is divided into groups of x bits where x is the least common multiple of r and m, an arbitrary first dataword selected from x/r groups of first datawords is divided into x/m, an m-bit second dataword is formed by appending r/(x/m)-bit data, obtained by dividing the first dataword into x/m, to the LSB or MSB side of one or other of the non-divided first datawords, and the word-converted m-bit second dataword is converted to an n-bit codeword (m&lt;n).

Data conversion method and apparatus imbedding pilot signal into

The method and apparatus records/reproduces multiple kinds of digital signals having different data amounts per unit time on a recording medium. The multiple kinds of digital signals are organized into a plurality of blocks. At least two of the multiple kinds of digital signals are organized into blocks having different lengths. A synchronizing signal is appended to each of the plurality of blocks. The synchronizing signal identifies a length of each of the plurality of blocks. This method an apparatus increase the recording rate, and is therefore suitable for higher density recording. In reproduction, synchronization protection is performed for variable synchronization periods based on the length of the blocks being reproduced.

Recording/reproducing apparatus for recording and reproducing multiple

A data conversion apparatus which converts an m-bit data into plural n-bit codes having different CDS values to obtain an intense spectrum at frequencies with a period of p bits has a CDS control signal generator which generates data of a known CDS in codeword with one period which is the least common multiple (q) of n and p, an error detector which detects differences between values of charge in codeword at intervals of (r) bits (where r is the greatest common divisor of n and p) and the data of the known CDS in codeword and detects a sum of absolute values (.DELTA.CDS) of the differences, and a minimum value hold circuit which selects a code having the smallest sum of absolute values (.DELTA.CDS), from the plural n-bit codes having different CDS values.

Growing community of inventors

Tokyo, Japan

Hideaki Kosaka