Fujitsu Corporation

Fujitsu Microelectronics Limited

Hideaki Konishi

Ryuji Shimizu

Junko Kumagai

Satoshi Masuda

Naofumi Kobayashi

Hitoshi Watanabe

Takahisa Hiraide

Daisuke Maruyama

Koichi Itaya

Hitoshi Yamanaka

Toshihito Shimizu

Osamu Ōkano

Kazuyuki Yamamura

Daisuke Tsukuda

Takeshi Doi

Naoko Karasawa

Yuko Katoh

Haruhiko Abe

Masayasu Hojo

In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

Delay failure test circuit

A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.

Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product

A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Method and apparatus for supporting designing of LSI, and computer product

An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

Testing apparatus and testing method for an integrated circuit, and integrated circuit

Growing community of inventors

Kawasaki, Japan

Hideaki Konishi