International Business Machines Corporation

Sap Se

Sap Ag

Hideaki Komatsu

Akira Koseki

Motohiro Kawahito

Moriyoshi Ohara

Takeshi Ogasawara

Toshiaki Yasue

Hiroshi Inoue

Takuya Nakaike

Takeo Yoshizawa

Tatsushi Inagaki

Takao Moriyama

Kazuaki Ishizaki

Toshio Suganuma

Kazunori Ogata

Yukihiko Sohda

Kiyokuni Kawachiya

Mikio Takeuchi

Shuichi Shimizu

Arquimedes Martinez Canedo

Tamiya Onodera

Masaki Kataoka

Toshiro Takase

Masana Murase

Rei Odaira

Kumiko Maeda

Munehiro Doi

Haruki Imai

Koichi Kajitani

Hiroyuki Momose

Michiaki Tatsubori

Hitomi Takahashi

Shu Shimizu

Goh Kondoh

Fumitomo Ohsawa

Gang Zhang

Hiroshi Dohji

Kohichi Kajitani

Toshio Nakatani

Kauaki Ishizaki

Tatshushi Inagaki

Kunio Tabata

Takeshi Oqasawara

Gyo Ohsawa

Osamu Gohda

Fimitomo Ohsawa

An extraction method for extracting a sub query to be converted to a program for processing stream data continuously inputted to a database, from a query including instructions, as sub queries, to be issued to a database management system. The extraction method includes receiving input of the query and a lower limit value of efficiency as processing time per unit memory increase amount. A calculating operation calculates a one memory increase amount and the efficiency using the memory increase amount and the processing time to be reduced. The method selects a sub query whose calculated efficiency is equal to or higher than the lower limit value and extracts the selected sub query as a conversion object on condition that the integrated memory increase amount is equal to or smaller than the maximum memory increase amount.

Extraction device, data processing system, and extraction method

A computer-implemented method for controlling data transfer for data processing includes: receiving a data set by a first processor; storing the data set in a buffer by the first processor; and transferring, from the buffer to a queue by the first processor, a batch data set including all data sets stored in the buffer during a time interval, under a condition that the queue is not accessed by a second processor while the transferring is being performed, wherein the batch data set is to be processed by the second processor. In the method, the time interval is adjusted depending on a state of the queue.

Controlling data transfer for data processing

An extraction device for extracting a sub query to be converted to a program for processing stream data continuously inputted to a database, from a query including instructions, as sub queries, to be issued to a database management system. The extraction device includes: an input unit; an operation unit for calculating the memory increase amount in a case of processing the stream data and the processing time to be reduced for each sub query, and calculating the efficiency by using them; and an extraction unit for selecting at least one sub query whose efficiency is equal to or higher than the lower limit value, integrating the memory increase amount calculated for the selected sub query, and on condition that the integrated memory increase amount is equal to or smaller than the maximum memory increase amount, extracting the selected sub query as a conversion object.

Traffic data while the system is in operation is collected for a certain time as a preprocess. Typical patterns are extracted from the collected traffic data. Next, stream programs are created for the individual typical patterns and stored for the future reference. Next, the IDs of alternative tasks for transition among different stream programs are stored. In actual system operation, the system measures traffic data regularly or at any time, compares the resultant patterns with the typical patterns, and selects a stream program corresponding to the closest typical pattern as the next phase. Program shutdown time when shifting from the stream program in the present phase to the next phase can be reduced by gradually shifting empty tasks in the present phase to the next stream program as alternative tasks in consideration of the cost of switching between tasks, the cost of transferring data among resources, and so on.

Computer system, method, and program

A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.

Merging sorted data arrays based on vector minimum, maximum, and permute instructions

System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators.

Simulation method, system, and program

A parallelization method, system and program. A program expressed by a block diagram or the like is divided into strands and a balance in calculation time is made among the strands. The functional blocks are divided into strands and the strand involving the maximum calculation time from a strand set is found. One or more movable blocks in the strand involving the maximum calculation time is found. The next step is obtaining calculation time of each strand after the movable block is moved to the strand in the input or output direction according to its property, and moving the block to a strand most largely reducing the calculation time of the strand having the maximum calculation time before the movement. This process loops until calculation time is no longer reduced. Strands are then transformed into source codes. Source codes are compiled and assigned to separate cores or processors for execution.

Parallelization method, system and program

A system is provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.

Profile-based global live-range splitting

A computer program product is provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph.

CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction.

Computer system and method of controlling computer system

A method converts a plurality of functional blocks into linear blocks such that the nonlinear blocks are divided into a plurality of states through switched linearization. The plurality of states generated by said switched linearization is then transitioned selectively based on a predetermined operational scenario. Each state is then tested separately to ensure that implementation of the states are safe. A first guard block is provided when a state is deemed unsafe such that the first guard block is enabled to cause a system shutdown so as to prevent further processing that can cause an unsafe result.

Control system design simulation using switched linearization

A method, system, and computer readable article of manufacture for simulating a mechanism system controlled by a plurality of electronic control units operating at different clock rates. The simulation system includes a mechanism system simulator; a plurality of electronic control unit emulators for electronically emulating the respective plurality of electronic control units, each thereby receiving an input signal with a time and giving an output signal with a time; and a scheduler for receiving and storing the output signals with the times from the plurality of electronic control unit emulators, and for providing, in response to a change in the output signal coming from the electronic control unit emulator and having a relatively late time, the output signal with a time preceding the relatively late time to the mechanism system simulator.

Control unit simulation method, system, and program

Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory&#x2014;except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Reduced data transfer during processor context switching

A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks.

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Yokohama, Japan

Hideaki Komatsu