Denso Corporation

Nippondenso Co., Ltd.

Hideaki Ishihara

Toshihiko Matsuoka

Yoshinori Teshima

Masahiro Kamiya

Kenji Yamada

Yasuyuki Ishikawa

Naoki Ito

Akira Suzuki

Katsutoyo Misawa

Kouichi Maeda

Akihiro Sasaki

Hiroshi Fujii

Kyouichi Suzuki

Hirofumi Abe

Shinichirou Taguchi

Masato Rinnai

Shinichi Noda

Haruyasu Sakishita

Nobutomo Takagi

Hirohiko Yamada

Akimasa Niwa

Yasushi Kanda

Kouji Ichikawa

Hiroshi Hayakawa

Susumu Tsuruta

Kazushi Matsuo

Chikara Kobayashi

Yukari Ishiguro

Shinichiro Taguchi

Yukari Sugiura

Sinichi Noda

Tengo Fujii

Hiroaki Tanaka

Tsuyoshi Yamamoto

Atsushi Kobayashi

Akira Takaoka

Masakiyo Horie

Tomonori Kimura

Koji Sakakibara

Harutsugu Fukumoto

Taiji Abe

Fan Wang

Yuukou Murase

Hiroyuki Obata

Koichi Kamabora

Yoshimitsu Honda

Takayuki Matsuda

Yoshinori Gotoh

Hiroshi Matsuda

Yoshinori Yunosawa

Kazuhiro Nakai

Akimitsu Inoue

Naoki Itoh

Youichi Fujita

Toshiharu Muramatsu

Katsurou Sekiya

Kunitaka Egawa

An opening area between twisted portions of a pair of twisted wires is arranged to be opposite to an opening area of an aperture antenna of each of communication apparatuses. Thus, the use of the pair of twisted wires permits division of electric power among the communication apparatuses and also communication of signals. In particular, among the opening areas between the twisted portions of the pair of twisted wires, only an opening area, which is in between the twisted portion and the twisted portion and is opposite to the aperture antenna, is formed to be larger than a different opening area. This provides a vehicular power line communication system and a transmitter in the system; the system strengthens electromagnetic induction connection between the transmitter and the receiver to permit power line communication.

Vehicular power line communication system and transmitter

A power conversion apparatus includes main circuits, in which switching elements are connected in parallel with diodes, respectively. An auxiliary circuit, which is formed of a series-connected second switching element and a capacitor, is connected in parallel with the diode operating as a freewheeling diode. The switching element of the main circuit, which is opposite to the auxiliary circuit, is set to turn on at a reference time. The second switching element of the auxiliary circuit is set to turn on in advance of the reference time by an interval of a discharging time period of the capacitor in a dead time period.

Power conversion apparatus

In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.

Communication slave and communication network system

A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus.

Memory management apparatus and method for same

A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Periodic signal processing apparatus

A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.

Microcomputer system

A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.

Data reception apparatus and microcomputer having the same

A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

Microcomputer system with reduced power consumption

A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.

Microcomputer and encoding system for executing peripheral function instructions

A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.

Communication system communication device and method for determining duty ratio of PWM control

A microcomputer and method are provided capable of restarting a rewrite program without the need for changing a mode using an external terminal when rewriting nonvolatile memory fails. A CPU of a microcomputer executes a rewrite program to clear FLASH status 0 of flash memory and rewrite all areas in it. The CPU finally writes a rewrite completion code to FLASH status 0. The CPU executes a determination program to read FLASH status 0 of the flash memory. The CPU reads ID status information when read data does not match the rewrite completion code. The CPU re-executes the rewrite program when the data matches ID status information.

Microcomputer for flash memory rewriting

A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.

Semiconductor integrated circuit device for providing series regulator

A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that operates based on the main clock signal, a signal output circuit that operates based on the sub clock signal and outputs a timing signal at a predetermined interval, and a voltage monitoring circuit that operates based on the sub clock signal and intermittently performs a voltage monitoring function in response to the timing signal. The sub oscillator operates independently of the main oscillator.

Microcomputer and control system having the same

A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.

Microcomputer and functional evaluation chip

A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Processor, microcomputer and method for controlling program of microcomputer

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Okazaki, Japan

Hideaki Ishihara