Kabushiki Kaisha Toshiba

Hideaki Harakawa

Akiko Nomachi

Makoto Honda

Hisashi Kaneko

Hirokazu Ezawa

Koichi Kokubun

Hiroshi Naruse

Hiroshi Takato

Hideto Matsuyama

Masanori Numano

Takahito Nagamatsu

Toshiaki Komukai

Kaori Yomogihara

Kazuhiro Murakami

Tadaomi Sakurai

Tatsuya Kishi

Masatoshi Yoshikawa

Keiji Hosotani

Jyunichi Ozeki

Satoshi Seto

Mari Otsuka

Hiroyuki Kamijiyo

According to one embodiment, a magnetoresistive element includes a storage layer having a variable and perpendicular magnetization, a tunnel barrier layer on the storage layer, a reference layer having an invariable and perpendicular magnetization on the tunnel barrier layer, a hard mask layer on the reference layer, and a sidewall spacer layer on sidewalls of the reference layer and the hard mask layer. An in-plane size of the reference layer is smaller than an in-plane size of the storage layer. A difference between the in-plane sizes of the storage layer and the reference layer is 2 nm or less. The sidewall spacer layer includes a material selected from a group of a diamond, DLC, BN, SiC, BC, AlOand AlN.

Magnetoresistive element and method of manufacturing the same

An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NFor HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed

A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si&#x2014;H concentration is smaller than N&#x2014;H concentration.

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.

Semiconductor device comprising transistor and capacitor and method of manufacturing the same

A method of manufacturing a semiconductor device according to one aspect of the present invention comprises: forming a gate insulation film on a semiconductor substrate in which element separation regions are formed; depositing a gate lower layer material on the semiconductor substrate via the gate insulation film; depositing a gate upper layer material, which is composed of a material different from the gate lower layer material, on the gate lower layer material; forming a gate comprising a gate upper layer and a gate lower layer by selectively processing the gate upper layer material and the gate lower layer material; increasing the size of the gate upper layer in a horizontal direction with respect to the semiconductor substrate by carrying out a chemical reaction processing treatment to which the gate upper layer has a higher reaction speed than the gate lower layer; forming an impurity implantation region by implanting ions into the semiconductor substrate using the gate upper layer as a mask; and forming a source/drain diffusion layer from the impurity implantation region by carrying out a thermal diffusion treatment.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.

Method for manufacturing semiconductor device

In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Semiconductor device manufacturing method permitting suppression of leak current through the PN junction

Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same

An inter-level insulating film is formed on a first Al film and a contact hole is formed to partly expose the first Al film. A TiW film is formed on the internal side surface of the contact hole and a W film is formed to form a conductive plug. After a TiN film and a second Al film are formed on the plug and inter-level insulating film, a resist mask used for etching the above films is formed in position corresponding to the plug. By use of this plug, the second Al film and TiN film are removed by RIE using Cl-series gas. Since the selective etching ratio of TiW film/Ti film is approx. 0.2, etching of the TiW film in the plug can be suppressed even if the mask is formed in position deviated from the upper portion of the plug. Therefore, after formation of the insulating film, occurrence of void can be prevented, thereby enhancing the reliability and service life of the interconnection structure.

Method of making a multilayer interconnection of semiconductor device

Growing community of inventors

Kawasaki, Japan

Hideaki Harakawa